Ultra-wideband communication apparatus and methods

Abstract

Apparatus and methods of ultra-wideband (UWB) communication are provided. In one embodiment, an ultra-wideband transmitter includes a processor configured to generate data for transmission in the form of a plurality of ultra-wideband pulses. The transmitter includes a FEC encoder that generates a code word based on the data. The FEC includes a plurality of cyclic shift registers configured to receive and process the data, a plurality of fixed connections between each of the plurality of cyclic shift registers and a plurality of XOR gates communicating with the plurality of fixed connections. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

1 . An ultra-wideband transmitter, comprising:
 a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband signals by the transmitter; and   a forward error correction encoder configured to generate a code word based on the data, the forward error correction encoder comprising:
 a plurality of cyclic shift registers configured to receive and process the data; 
 a plurality of fixed connections between each of the plurality of cyclic shift registers; and 
 a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates. 
   
     
     
         2 . The ultra-wideband transmitter of  claim 1 , wherein each of the ultra-wideband signals may range in duration from about 10 picoseconds to about one microsecond. 
     
     
         3 . The ultra-wideband transmitter of  claim 1 , wherein each ultra-wideband signal occupies at least 500 megahertz of a radio frequency spectrum. 
     
     
         4 . The ultra-wideband transmitter of  claim 1 , further comprising a register configured to store an output of each of the plurality of XOR gates. 
     
     
         5 . The ultra-wideband transmitter of  claim 1 , wherein the code word is generated using a parity matrix. 
     
     
         6 . The ultra-wideband transmitter of  claim 5 , wherein the parity matrix comprises a dual diagonal matrix. 
     
     
         7 . The ultra-wideband transmitter of  claim 5 , wherein the parity matrix comprises a matrix of cyclic matrices. 
     
     
         8 . The ultra-wideband transmitter of  claim 7 , wherein each of the cyclic matrices are generated from an identity matrix and a permutation vector. 
     
     
         9 . An ultra-wideband transmitter, comprising:
 a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband pulses by the transmitter; and   a forward error correction encoder configured to generate a code word based on the data, with the code word generated using a parity matrix comprising a matrix of cyclic matrices, where each of the cyclic matrices are generated from an identity matrix and a permutation vector;   the forward error correction encoder comprising:
 a plurality of cyclic shift registers configured to receive and process the data; 
 a plurality of fixed connections between each of the plurality of cyclic shift registers; and 
 a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates. 
   
     
     
         10 . The ultra-wideband transmitter of  claim 9 , further comprising a register configured to store an output of each of the plurality of XOR gates. 
     
     
         11 . The ultra-wideband transmitter of  claim 9 , wherein each of the ultra-wideband signals may range in duration from about 10 picoseconds to about one microsecond. 
     
     
         12 . The ultra-wideband transmitter of  claim 9 , wherein each ultra-wideband signal occupies at least 500 megahertz of a radio frequency spectrum. 
     
     
         13 . An ultra-wideband transmitter, comprising:
 a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband signals by the transmitter; and   a forward error correction encoder configured to generate a code word based on the data, where the code word is generated using a parity matrix, with the parity matrix comprising a dual diagonal matrix;   the forward error correction encoder comprising:
 a plurality of cyclic shift registers configured to receive and process the data; 
 a plurality of fixed connections between each of the plurality of cyclic shift registers; and 
 a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates. 
   
     
     
         14 . The ultra-wideband transmitter of  claim 13 , wherein each of the ultra-wideband signals may range in duration from about 10 picoseconds to about one microsecond. 
     
     
         15 . The ultra-wideband transmitter of  claim 13 , wherein each ultra-wideband signal occupies at least 500 megahertz of a radio frequency spectrum. 
     
     
         16 . The ultra-wideband transmitter of  claim 13 , further comprising a register configured to store an output of each of the plurality of XOR gates.