US2008163019A1PendingUtilityA1

Scanning Latches Using Selecting Array

Assignee: MARTIN ANDREW KENNETHPriority: Jul 22, 2004Filed: Mar 3, 2008Published: Jul 3, 2008
Est. expiryJul 22, 2024(expired)· nominal 20-yr term from priority
G11C 29/32G11C 2029/3202G01R 31/318572G11C 11/41
41
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Claims

Abstract

A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.

Claims

exact text as granted — not AI-modified
1 . A system for accessing data from multiple latches, the system comprising:
 multiple data flow paths composed of multiple latches having intervening logic circuits, the latches functionally composed of holding devices for logic circuit data;   selective interconnects coupling latches in different data flow paths of the multiple data flow paths; and   a data accessing matrix coupled to two or more latches in two or more data flow paths by switching devices, the switching devices being activated by a line selector that activates the switching devices along a column of the data accessing matrix, wherein the contents of all latches in the column are output to multiple data lines along rows of the data accessing matrix.   
   
   
       2 . The system of  claim 1 , further comprising:
 means for selecting one of the data line rows of the data accessing matrix.   
   
   
       3 . The system of  claim 1 , further comprising:
 an input/output (I/O) buffer coupled to the data lines, wherein data read from the latches is transmitted via the data lines to the I/O buffer.   
   
   
       4 . The system of  claim 1 , wherein each of the latches is composed of feedback coupled inverters. 
   
   
       5 . The system of  claim 1 , wherein the switching devices are transistors. 
   
   
       6 . The system of  claim 1 , further comprising:
 a pre-charger coupled to each data line; and   a separate discharge switch coupling each of the latches to ground, wherein if a latch holds a first logical value, then the data line that is coupled to that latch is discharged, and wherein if that latch holds a second logical value, then the data line coupled to that latch remains charged.   
   
   
       7 . The system of  claim 1 , further comprising:
 at least one read select line and at least one write select line coupled to a line selector;   a read switch controlled by one of the read select lines, the read switch coupling one of the latches to one of the data lines; and   a write switch controlled by one of the write select lines, the write switch coupling the same one of the latches to the same one of the data lines, wherein data is read from the latch to the data line by closing the read switch while the write switch is open, and wherein data is written from the data line to the latch by closing the write switch while the read switch is open.

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