Semiconductor device having fuse circuit on cell region and method of fabricating the same

Abstract

A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is possible to reduce the size of a semiconductor chip.

1 . A method of fabricating a semiconductor device, the method comprising:
 forming a lower structure having a pad on a semiconductor substrate, the lower structure performing the functions of a memory and being divided into a cell region and a peripheral region;   forming a passivation layer on the lower structure to cover the semiconductor substrate except for the pad; and   forming a fuse pattern overlying the passivation layer in the cell region.   
   
   
       2 . The method of  claim 1 , wherein the lower structure is a DRAM circuit that performs the functions of a memory. 
   
   
       3 . The method of  claim 1 , further comprising forming a first insulating layer on the passivation layer, the first insulating layer and the passivation layer having an opening therethrough to expose the pad. 
   
   
       4 . The method of  claim 3 , wherein the first insulating layer is a single layer or a multi-layer formed of one selected from among a high density plasma (HDP) oxide layer, benzocyclobutene (BCB), polybenzoxazole (PBO), a polyimide and combinations thereof. 
   
   
       5 . The method of  claim 3 , further comprising:
 forming a via hole extending through the first insulating layer and the passivation layer to be connected to the lower structure; and   filling the via hole with a conductive material to form a plug.   
   
   
       6 . The method of  claim 1 , wherein the pad is located in the peripheral region, the method further comprising:
 forming a pad redistribution pattern on the passivation layer; and   forming a peripheral bond pad in the cell region, wherein the peripheral bond pad and the pad are electrically connected by the pad redistribution layer.   
   
   
       7 . A method of making a semiconductor device comprising:
 providing a semiconductor substrate having a lower structure formed thereon, the lower structure having a pad;   forming a first passivation layer on the lower structure, the first passivation layer having an opening therein to expose the pad; and   forming a fuse pattern located above the first passivation layer and electrically connected to the lower structure,   wherein the semiconductor substrate has a cell region and a peripheral region, and wherein the fuse pattern is formed in the cell region.   
   
   
       8 . The method of  claim 7 , further comprising forming a second passivation layer overlying the fuse pattern. 
   
   
       9 . The method of  claim 7 , further comprising forming a pad redistribution pattern on the first passivation layer, wherein the pad redistribution pattern is electrically connected to the lower structure via a plug formed through the first passivation layer.