Method for fabricating semiconductor package

Abstract

A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At least one first opening is formed on the first circuit layer corresponding to the second opening. A plurality of finger holes corresponding to bond fingers on the first circuit layer are formed in the core layer. A through opening is formed in the core layer and communicates with the first and second openings. At least one chip is mounted on the first circuit layer and covers the first opening, with its active surface being exposed to the first opening. An encapsulant is formed to fill the first and second openings and the through opening and encapsulate the chip.

1 : A method for fabricating a semiconductor package, comprising the steps of:
 preparing a substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first circuit layer and the second circuit layer;   forming at least one second opening on the second circuit layer, and forming at least one first opening on the first circuit layer at a position corresponding to the second opening;   forming a plurality of finger holes in the core layer at positions corresponding to a plurality of bond fingers formed on the first circuit layer;   forming a through opening in the core layer, allowing the through opening to communicate with the first opening of the first circuit layer and the second opening of the second circuit layer;   mounting at least one chip on the first circuit layer of the substrate, allowing the chip to cover the first opening and allowing an active surface of the chip to be exposed to the first opening;   forming a plurality of bonding wires to electrically connect the active surface of the chip to the plurality of bond fingers on the first circuit layer through the finger holes; and   forming an encapsulant on the substrate to fill the first and second openings and the through opening and encapsulate the chip and the bonding wires.   
     
     
         2 : The method of  claim 1 , wherein the plurality of bonding wires are inserted in the finger holes to be connected to the bond fingers. 
     
     
         3 : The method of  claim 1 , wherein the through opening of the core layer communicates with the finger holes. 
     
     
         4 : The method of  claim 1 , wherein the finger holes of the core layer are formed by laser drilling. 
     
     
         5 : The method of  claim 1 , wherein the through opening of the core layer is formed by using a router. 
     
     
         6 : The method of  claim 1 , wherein the first opening of the first circuit layer and the second opening of the second circuit layer are formed by etching. 
     
     
         7 : The method of  claim 1 , wherein a nickel (Ni)/gold Au) layer is formed on the bond fingers respectively. 
     
     
         8 : The method of  claim 7 , wherein the Ni/Au layer is formed by plating. 
     
     
         9 : The method of  claim 1 , wherein the bonding wires are completely received in the through opening of the substrate. 
     
     
         10 : The method of  claim 1 , wherein the height of the encapsulant filling the first and second openings and the through opening is equal to or smaller than the thickness of the substrate. 
     
     
         11 : The method of  claim 1 , wherein the core layer is further formed with a plurality of conductive vias for electrically connecting the first and second circuit layers to each other. 
     
     
         12 : The method of  claim 1 , further comprising implanting a plurality of solder balls on the substrate. 
     
     
         13 - 20 . (canceled)