Physical alignment features on integrated circuit devices for accurate die-in-substrate embedding

Abstract

A method of packaging an integrated circuit die including forming a mask window having a first aperture with a first set of alignment edges and forming an alignment feature on an uppermost surface of the integrated circuit die where the alignment feature has a second set of alignment edges. The alignment feature is inserted into the first aperture. The integrated circuit die is mechanically biased until the first and second set of alignment edges are in physical contact with one another and the alignment feature is secured into the mask window, thus forming an integrated circuit die assembly.

1 . A method of packaging an integrated circuit die, the method comprising:
 forming a mask window having a first aperture, the first aperture having a first set of alignment edges;   forming an alignment feature on an uppermost surface of the integrated circuit die, the alignment feature having a second set of alignment edges;   inserting the alignment feature into the first aperture;   mechanically biasing the integrated circuit die until the first and second set of alignment edges are in physical contact with one another; and   securing the alignment feature into the mask window, thus forming an integrated circuit die assembly.   
     
     
         2 . The method of  claim 1  further comprising:
 forming a windowed substrate having a second aperture, the second aperture being larger than a size of the integrated circuit die;   placing the windowed substrate over the integrated circuit secured onto the integrated circuit die assembly; and   substantially filling a spacing gap between the integrated circuit die and the second aperture.   
     
     
         3 . The method  claim 2  further comprising:
 removing the alignment feature from the integrated circuit die after substantially filling the spacing gap.   
     
     
         4 . The method of  claim 1  further comprising chamfering an intersection of each of the first and second set of alignment edges. 
     
     
         5 . The method of  claim 1  further comprising selecting a material for securing the alignment feature into the mask window to be an adhesive. 
     
     
         6 . A method of packaging an integrated circuit die, the method comprising:
 forming an alignment feature on an uppermost surface of the integrated circuit die, the alignment feature having a first set of positioning features;   inserting the alignment feature into a mask window having a first aperture, the first aperture having a second set of positioning features;   mechanically biasing the integrated circuit die until the first and second set of positioning features are in physical contact with one another;   placing a windowed substrate over the integrated circuit, the windowed substrate having a second aperture being larger than a size of the integrated circuit die; and   substantially filling a spacing gap between the integrated circuit die and the second aperture.   
     
     
         7 . The method of  claim 6  further comprising:
 removing the alignment feature from the integrated circuit die after substantially filling the spacing gap.   
     
     
         8 . The method of  claim 6  wherein the first set of positioning features is selected to be edges of the alignment feature and the second set of positioning features is selected to be edges of the first aperture. 
     
     
         9 . The method of  claim 9  further comprising chamfering an intersection of each of the first and second set of edges. 
     
     
         10 . The method of  claim 6  further comprising securing the alignment feature into the mask window prior to placing the windowed substrate over the integrated circuit. 
     
     
         11 . A method of packaging a plurality of integrated circuit dice, the method comprising:
 forming an alignment feature on an uppermost surface of each of the plurality of integrated circuit dice, each of the alignment features having a first set of positioning features;   inserting each of the alignment features into a mask window having a plurality of first apertures, each one of the plurality of first apertures being larger than respective ones of the plurality of alignment features and each of the plurality of first apertures further having a second set of positioning features;   mechanically biasing each the plurality of integrated circuit dice until the first and second set of positioning features are all in physical contact with one another;   placing a windowed substrate over the plurality integrated circuit dice, the windowed substrate having a plurality of second apertures, each one of the plurality of second apertures being larger than respective ones of the plurality of integrated circuit dice; and   substantially filling a spacing gap between each of the integrated circuit dice and the respective second aperture.   
     
     
         12 . The method of  claim 11  further comprising:
 removing each of the alignment features from the plurality of integrated circuit dice after substantially filling the spacing gaps.   
     
     
         13 . The method of  claim 11  wherein the first set of positioning features is selected to be edges of each of the alignment features and the second set of positioning features is selected to be edges of the each of the plurality first apertures. 
     
     
         14 . The method of  claim 13  further comprising chamfering an intersection of each of the first and second sets of alignment edges. 
     
     
         15 . The method of  claim 11  further comprising securing each of the alignment features into the mask window prior to placing the windowed substrate over the plurality of integrated circuit dice.