Operating method of non-volatile memory

Abstract

A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.

What is claimed is: 
     
         1 . An operating method suitable for operating a memory cell array including a plurality of memory cells on a substrate, wherein each memory cell comprises a select gate on the substrate; two floating gates on both sides of the select gate, a top surface of the two floating gates being higher than that of the select gate, such that a hollow structure is formed on the select gate between the two floating gates; a control gate on the substrate covering the select gate and the two floating gates and filling the hollow structure; a doped region in the substrate on one side of the two floating gates opposite to the select gate, wherein the two adjacent memory cells share the same doped region; a plurality of bit lines arranged in parallel in the row direction and connecting the doped regions of memory cells in the same row respectively; a plurality of word lines arranged in parallel in the column direction and connecting the control gates of memory cells in the same column respectively; a plurality of select gate lines arranged in parallel in the row direction and connecting the control gates of memory cells in the same row respectively, the operating method comprising:
 during programming operation, applying a first voltage to the first bit line coupled to the selected memory cell, applying a second voltage to the second bit line coupled to the selected memory cell, applying a third voltage to the word line coupled to the selected memory cell and applying a fourth voltage to the select gate line coupled to the selected memory cell, so as to store one data in the floating gate of the selected memory cell close to the side of the first bit line using a source-side injection effect, wherein the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.   
     
     
         2 . The operating method as claimed in  claim 1 , further comprising:
 during an erasing operation, applying a fifth voltage to the first bit line coupled to the selected memory cell and applying a sixth voltage to the word line coupled to the selected memory cell so that the floating gate of the selected memory cell close to the side of the first bit line can be erased using F-N tunneling, wherein the difference between the fifth voltage and the sixth voltage is larger than 10 V.   
     
     
         3 . The operating method as claimed in  claim 2 , further comprising:
 during reading operation, applying a seventh voltage to the first bit line coupled to the selected memory cell, applying an eighth voltage to the second bit line coupled to the selected memory cell, applying a ninth voltage to the word line coupled to the selected memory cell, and applying a tenth voltage to the select gate line coupled to the selected memory cell, so as to read the data stored in the floating gate of the selected memory cell close to the side of the first bit line, wherein the eighth voltage is higher than the ninth voltage, and the ninth voltage is higher than the seventh voltage.   
     
     
         4 . The operating method as claimed in  claim 3 , further comprising applying 0 V voltage to non-selected select gate lines, non-selected word lines and non-selected bit lines. 
     
     
         5 . The operating method as claimed in  claim 3 , wherein the first voltage is 6V; the second voltage is 0 V; the third voltage is 8 V; and the fourth voltage is 4 V. 
     
     
         6 . The operating method as claimed in  claim 3 , wherein the fifth voltage is 5 V and the sixth voltage is −12 V. 
     
     
         7 . The operating method as claimed in  claim 3 , wherein the seventh voltage is 0 V; the eighth voltage is 5 V; the ninth voltage is 3 V; and the tenth voltage is 4 V