Memory having storage locations within a common volume of phase change material

Abstract

A memory includes a volume of phase change material, a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material, and a second transistor coupled to the volume of phase change material for accessing a second storage location within the volume of phase change material.

1 . An integrated circuit comprising:
 a volume of phase change material;   a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material; and   a second transistor coupled to the volume of phase change material for accessing a second storage location within the volume of phase change material.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the first transistor and the second transistor are in the same layer. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the first transistor and the second transistor are adjacent. 
     
     
         4 . The integrated circuit of  claim 1 , further comprising:
 a third transistor coupled to the volume of phase change material for accessing a third storage location within the volume of phase change material; and   a fourth transistor coupled to the volume of phase change material for accessing a fourth storage location within the volume of phase change material,   wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are in the same layer.   
     
     
         5 . The integrated circuit of  claim 1 , wherein the volume of phase change material comprises a phase change material super via including a core comprising a material different from the phase change material. 
     
     
         6 . The integrated circuit of  claim 5 , wherein the core comprises a stack of at least two different conductive materials. 
     
     
         7 . The integrated circuit of  claim 6 , wherein the stack comprises one of a concentrically arranged stack, a horizontal layer stack, and a cone shaped stack. 
     
     
         8 . The integrated circuit of  claim 1 , wherein the volume of phase change material comprises a stack of at least two different phase change materials. 
     
     
         9 . The integrated circuit of  claim 8 , wherein the stack comprises one of a concentrically arranged stack, a horizontal layer stack, and a cone shaped stack. 
     
     
         10 . The integrated circuit of  claim 1 , further comprising:
 a first heater contact coupled between the first transistor and the volume of phase change material; and   a second heater contact coupled between the second transistor and the volume of phase change material.   
     
     
         11 . A memory comprising:
 a phase change material super via;   a first transistor coupled to the super via for accessing a first storage location within the super via; and   a second transistor coupled to the super via for accessing a second storage location within the super via.   
     
     
         12 . The memory of  claim 11 , wherein the phase change material super via comprises a core comprising a material different from the phase change material. 
     
     
         13 . The memory of  claim 11 , further comprising:
 a first word line coupled to a gate of the first transistor;   a second word line coupled to a gate of the second transistor; and   a bit line coupled to the phase change material super via.   
     
     
         14 . The memory of  claim 13 , wherein the bit line is perpendicular to the first word line and the second word line. 
     
     
         15 . The memory of  claim 13 , further comprising:
 a ground via coupled to the first transistor and the second transistor.   
     
     
         16 . The memory of  claim 13 , further comprising:
 a ground plate coupled to the first transistor and the second transistor.   
     
     
         17 . The memory of  claim 13 , further comprising:
 a first ground line coupled to the first transistor; and   a second ground line coupled to the second transistor.   
     
     
         18 . A phase change memory comprising:
 means for accessing a first storage location;   means for accessing a second storage location; and   means for sharing a common volume of phase change material to provide the first storage location and the second storage location.   
     
     
         19 . The memory of  claim 18 , further comprising:
 means for simultaneously accessing the first storage location and the second storage location.   
     
     
         20 . The memory of  claim 18 , further comprising:
 means for heating phase change material in the first storage location for changing a state of the phase change material in the first storage location.   
     
     
         21 . A method for fabricating a memory, the method comprising:
 fabricating a first transistor for accessing a first storage location;   fabricating a second transistor for accessing a second storage location; and   fabricating a phase change material super via to provide the first storage location and the second storage location.   
     
     
         22 . The method of  claim 22 , further comprising:
 fabricating a first heater contact coupled between the first transistor and the first storage location; and   fabricating a second heater contact coupled between the second transistor and the second storage location.   
     
     
         23 . The method of  claim 22 , further comprising:
 fabricating a first word line coupled to a gate of the first transistor; and   fabricating a second word line coupled to a gate of the second transistor.   
     
     
         24 . The method of  claim 22 , further comprising:
 fabricating a bit line coupled to the phase change material super via.   
     
     
         25 . The method of  claim 22 , further comprising:
 fabricating a first bit line coupled to the first transistor; and   fabricating a second bit line coupled to the second transistor.