Methods of forming stepped bumps and structures formed thereby

Abstract

Methods of forming a microelectronic device and associated structures are described. Those methods may comprise forming a die-side conductive interconnect on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion.

1 . A structure comprising:
 a die-side conductive interconnect disposed on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion; and   a solder bump disposed on a package substrate, wherein the solder bump is coupled with the columnar portion of the conductive interconnect.   
   
   
       2 . The structure of  claim 1  wherein the diameter of the columnar portion is about 50 percent to about 80 percent of the diameter of the base portion. 
   
   
       3 . The structure of  claim 1  wherein an angle between the base portion and the columnar portion is about 80 to about 100 degrees. 
   
   
       4 . The structure of  claim 1  wherein the die-side conductive interconnect comprises copper. 
   
   
       5 . The structure of  claim 1  further comprising wherein the solder bump wets at least 50 percent of a sidewall of the conductive interconnect. 
   
   
       6 . The structure of  claim 1  wherein the solder bump comprises a lead free solder bump. 
   
   
       7 . The structure of  claim 1  further comprising wherein the base portion of the die-side conductive interconnect is conductively coupled to a die disposed within the substrate, and wherein the substrate further comprises a passivation layer. 
   
   
       8 . The structure of  claim 1  wherein an underfill material is disposed between a surface of the substrate and a surface of the package substrate. 
   
   
       9 . The structure of  claim 7  further comprising wherein the passivation layer is disposed on a device interconnect layer. 
   
   
       10 . The structure of  claim 9  wherein the device interconnect layer comprises a low k ILD. 
   
   
       11 . The structure of  claim 1  wherein the structure comprises a portion of a joint structure. 
   
   
       12 . The structure of  claim 1  further comprising a system comprising:
 the joint structure;   a bus communicatively coupled to the joint structure; and   a DRAM communicatively coupled to the bus.