US2008157231A1PendingUtilityA1

Gate structure

Assignee: UNITED MICROELECTRONICS CORPPriority: Nov 8, 2005Filed: Mar 11, 2008Published: Jul 3, 2008
Est. expiryNov 8, 2025(expired)· nominal 20-yr term from priority
H10D 64/01318H10W 20/093H10D 64/01344H10D 64/693H10D 64/691H10D 64/667
49
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Claims

Abstract

A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A gate structure, comprising:
 an interface layer disposed on a substrate;   a high dielectric constant (K) gate dielectric layer disposed on the interface layer;   a barrier layer disposed on the high-K gate dielectric layer; and   a metal layer disposed on the barrier layer.   
     
     
         2 . The gate structure of  claim 1 , wherein the interface layer comprises a silicon oxynitride layer. 
     
     
         3 . The gate structure of  claim 1 , wherein the interface layer has a nitrogen concentration profile that decreases progressively toward the substrate. 
     
     
         4 . The gate structure of  claim 1 , wherein the interface layer has a thickness smaller than 7 Å. 
     
     
         5 . The gate structure of  claim 1 , wherein the nitrogen content in the interface layer is between 0.5˜5% by weight. 
     
     
         6 . The gate structure of  claim 1 , wherein the material constituting the high-K gate dielectric layer comprises tantalum oxide, zirconium oxide, hafnium oxide, aluminum oxide, hafnium silicide and titanium oxide. 
     
     
         7 . The gate structure of  claim 1 , wherein the high-K gate dielectric layer has a thickness between 20 Ř40 Å. 
     
     
         8 . The gate structure of  claim 1 , wherein the material constituting the metal layer comprises aluminum, platinum, tungsten, iridium, molybdenum, molybdenum nitride, nickel, nickel silicide, titanium, titanium nitride, titanium silicide, tantalum and tantalum nitride. 
     
     
         9 . The gate structure of  claim 1 , wherein the material constituting the barrier layer comprises hafnium, titanium nitride, tantalum nitride and titanium nitride/titanium.

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