Tri-gate device with conformal pvd workfunction metal on its three-dimensional body and fabrication method thereof

Abstract

A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.

1 . A semiconductor apparatus comprising:
 a semiconductor body having a top surface and laterally opposite sidewalls;   a metal gate with approximately equal thickness on the top surface and the laterally opposite sidewalls, wherein the metal gate contains columnar grains.   
   
   
       2 . The apparatus of  claim 1 , wherein a dielectric layer is positioned between the semiconductor body and the metal gate. 
   
   
       3 . The apparatus of  claim 2 , wherein the dielectric layer comprises at least one of a silicon oxide, lanthanum oxide, tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, lead-zirconate-titanate, barium-strontium-titanate, or aluminum oxide. 
   
   
       4 . The apparatus of  claim 1 , wherein a polysilicon layer is deposited on the metal gate. 
   
   
       5 . A semiconductor apparatus comprising:
 a semiconductor body having a top surface and laterally opposite sidewalls;   a dielectric layer on the top surface and the laterally opposite sidewalls of the semiconductor body;   a metal gate layer with approximately equal thickness on a top surface and laterally opposite sidewalls of the dielectric layer, wherein the metal gate layer contains columnar grains; and   a polysilicon layer on the metal gate layer.   
   
   
       6 . The apparatus of  claim 5 , wherein the polysilicon layer is doped. 
   
   
       7 . The apparatus of  claim 5 , wherein the thickness of the metal gate layer on the top surface and laterally opposite sidewalls of the dielectric layer match within a maximum deviation of +/−10%.