Transistor, fabricating method thereof and flat panel display therewith

Abstract

A transistor includes a substrate, an active region including a source region, a channel region, and a drain region which are crystallized using an SGS crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different from each other, a gate insulating layer formed on the active region, and a gate electrode formed on the gate insulating layer.

1 . A transistor, comprising:
 a substrate;   an active region including a source region, a channel region, and a drain region, which are crystallized using an SGS (Super Grain Silicon) crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different from each other;   a gate insulating layer formed on the active region; and   a gate electrode formed on the gate insulating layer.   
     
     
         2 . The transistor as claimed in  claim 1 , wherein a grain boundary size of the first annealed portion is smaller than that of the second annealed portion. 
     
     
         3 . The transistor as claimed in  claim 1 , wherein the active region includes metal catalysts. 
     
     
         4 . The transistor as claimed in  claim 3 , wherein the concentration of the metal catalysts in the first annealed portion is higher than that of the second annealed portion. 
     
     
         5 . The transistor as claimed in  claim 3 , wherein the metal catalyst is one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt, or any combinations thereof. 
     
     
         6 . The transistor as claimed in  claim 1 , wherein the source region and the drain region are doped with a P-type dopant. 
     
     
         7 . The transistor as claimed in  claim 1 , wherein the source region and the drain region are doped with an N-type dopant. 
     
     
         8 . The transistor as claimed in  claim 1 , wherein the gate electrode is one of MoW, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or any combinations thereof. 
     
     
         9 . The transistor as claimed in  claim 1 , further comprising a buffer layer formed between the substrate and the active region. 
     
     
         10 . The transistor as claimed in  claim 1 , further comprising:
 an inter-layer dielectric layer formed on a surface of the gate insulating layer and the gate electrode;   a source electrode connected to the source region and penetrating through the inter-layer dielectric layer and gate insulating layer; and   a drain electrode connected to the drain region and penetrating through the inter-layer dielectric layer and the gate insulating layer.   
     
     
         11 . The transistor as claimed in  claim 1 , wherein a grain boundary does not exist in the active region. 
     
     
         12 . The transistor as claimed in  claim 1 , wherein at least one grain boundary exists in the active region. 
     
     
         13 . A fabricating method of the transistor, comprising:
 preparing a substrate,   forming an amorphous silicon layer on the substrate;   forming a capping layer on the amorphous silicon layer;   forming a metal catalyst layer on the capping layer;   performing a first annealing process to crystallize amorphous silicon of the amorphous silicon layer into first annealed polycrystalline silicon using an SGS (Super Grain Silicon) crystallization method wherein metal catalysts of the metal catalyst layer diffuse as far as the amorphous silicon by penetrating through the capping layer;   removing the metal catalyst layer and the capping layer; and   performing a second annealing process wherein the metal catalyst crystallizes the amorphous silicon into second annealed polycrystalline silicon using the SGS crystallization method to form a polycrystalline silicon layer.   
     
     
         14 . The fabricating method of the transistor as claimed in  claim 13 , further comprising:
 forming a semiconductor layer by patterning the polycrystalline silicon layer; and   forming a gate insulating layer, a gate electrode, an inter-layer dielectric layer, and a source/drain electrode on the substrate.   
     
     
         15 . The fabricating method of the transistor as claimed in  claim 13 , wherein during the removing of the metal catalyst layer and the capping layer, the metal catalyst layer and the capping layer are removed once the amorphous silicon is crystallized so that a respective grain boundary size is smaller than half of an average distance between the metal catalysts. 
     
     
         16 . The fabricating method of the transistor as claimed in  claim 13 , further comprising:
 forming a buffer layer before forming of the amorphous silicon layer on the substrate.   
     
     
         17 . The fabricating method of the transistor as claimed in  claim 13 , wherein crystallinity of the polycrystalline silicon formed by the first annealing process is different from that of the polycrystalline silicon formed by the second annealing process. 
     
     
         18 . The fabricating method of the transistor as claimed in  claim 13 , wherein a grain boundary size of the polycrystalline silicon formed by the first annealing process is smaller than that of the polycrystalline silicon formed by the second annealing process. 
     
     
         19 . The fabricating method of the transistor as claimed in  claim 13 , wherein the concentration of the metal catalyst of the polycrystalline silicon formed by the first annealing process is higher than that of the metal catalyst of the polycrystalline silicon formed by the second annealing process. 
     
     
         20 . The fabricating method of the transistor as claimed in  claim 13 , wherein a grain boundary does not exist in the second annealed polycrystalline silicon. 
     
     
         21 . The fabricating method of the transistor as claimed in  claim 13 , wherein at least one grain boundary exists in the second annealed polycrystalline silicon. 
     
     
         22 . The fabricating method of the transistor as claimed in  claim 13 , wherein the metal catalyst layer is one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt, or any combinations thereof. 
     
     
         23 . The fabricating method of the transistor as claimed in  claim 13 , wherein the capping layer is an insulating layer. 
     
     
         24 . The fabricating method of the transistor as claimed in  claim 13 , wherein the capping layer is one of an oxide film, a nitride film, or any combinations thereof. 
     
     
         25 . The fabricating method of the transistor as claimed in  claim 13 , wherein the oxide film is one of silicon dioxide (SiO 2 ), aluminum oxide (alumina, Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (zirconia, ZrO 2 ), or any combinations thereof. 
     
     
         26 . A flat panel display device, comprising:
 the transistor manufactured by the method of  claim 13 .   
     
     
         27 . The method of  claim 13 , wherein the first annealing process occurs between about 500° C. to about 650° C. and the second annealing process occurs between about 550° C. to about 800° C.