Manufacturing method of non-volatile memory

Abstract

A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

What is claimed is: 
     
         1 . A manufacturing method of the non-volatile memory, comprising:
 providing a substrate;   forming a first memory unit on the substrate, wherein the first memory unit, from the substrate up, comprises a dielectric layer, a floating gate, an integrate dielectric layer and a first control gate;   forming a charge trapping structure on the substrate;   forming a conductive layer on the substrate;   removing a portion of the conductive layer to form a second control gate on one sidewall of the first memory unit, wherein the charge trapping structure and the second control gate together form a second memory unit; and   forming two doping regions at a side of the first memory unit not adjacent to the second memory unit and a side of the second memory unit not adjacent to the first memory unit.   
     
     
         2 . The method of  claim 1 , further comprising forming an N-type well region in the substrate before the step of forming the first memory unit. 
     
     
         3 . The method of  claim 2 , wherein the two doping regions are P-type doping regions. 
     
     
         4 . The method of  claim 1 , wherein the charge trapping structure, from the substrate up, comprises a tunneling dielectric layer, a charge trapping layer and a barrier dielectric layer. 
     
     
         5 . The method of  claim 4 , wherein the material of the charge trapping layer comprises silicon nitride. 
     
     
         6 . The method of  claim 1 , wherein the method for removing a portion of the conductive layer comprises:
 self-aligned etching the conductive layer to form the side wall spacers on both sides of the first memory unit by using the charge trapping as an etching stop layer;   forming a patterned photoresist layer on the substrate to cover the conductive layer on the sidewall of the first memory unit; and   removing the exposed part of the conductive layer by using the patterned photoresist layer as a mask.   
     
     
         7 . The method of  claim 6 , wherein the method for removing the exposed part of the conductive layer comprises a non-isotropic etching process.