Non-Volatile Memory In CMOS Logic Process

Abstract

A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).

1 . A method of fabricating a non-volatile memory cell comprising:
 forming a first active region, a second active region and a third active region in a semiconductor substrate;   forming an access transistor in the first active region of the semiconductor substrate;   forming a control capacitor in the second active region of the semiconductor substrate, the control capacitor including a diffusion region located in the second active region; and   forming a programming transistor in the third active region of the semiconductor substrate, wherein the steps of forming the access transistor, the control capacitor and the programming transistor comprise forming a floating gate electrode, which is shared by the access transistor, the control capacitor and the programming transistor.   
     
     
         2 . The method of  claim 1 , further comprising fabricating the non-volatile memory cell with a conventional logic process, wherein the floating gate electrode is formed from a sole conductive gate layer of the conventional logic process. 
     
     
         3 . The method of  claim 1 , wherein the step of forming the first, second and third active regions comprise:
 causing the first and second active regions to have a first conductivity type; and   causing the third active region of a second conductivity type, opposite the first conductivity type.   
     
     
         4 . The method of  claim 3 , further comprising selecting the first and second implants to have the second conductivity type and selecting the third implant to have the first conductivity type. 
     
     
         5 . The method of  claim 1 , further comprising forming a gate dielectric layer, which is located between the common floating gate electrode and the semiconductor substrate. 
     
     
         6 . The method of  claim 1 , wherein the third implant comprises a source region that extends under the floating gate electrode and a drain region that extends under the floating gate electrode, the method further comprising electrically shorting the source region and the drain region. 
     
     
         7 . The method of  claim 6 , further comprising causing the source region and the drain region to be continuous within the third active region. 
     
     
         8 . The method of  claim 6 , further comprising causing a continuous depletion region to surround the source region and the drain region. 
     
     
         9 . The method of  claim 1 , further comprising causing the first active region to be continuous with the second active region. 
     
     
         10 . The method of  claim 1 , wherein the second implant extends under the floating gate electrode further than the first implant extends under the floating gate electrode. 
     
     
         11 . The method of  claim 10 , wherein the third implant extends under the floating gate electrode further than the first implant extends under the floating gate electrode.