Operating method of non-volatile memory

Abstract

A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

What is claimed is: 
     
         1 . An operating method of a P-type channel memory, the P-type channel memory comprising: an N-type well region disposed in a substrate, a memory cell disposed on the N-type well region and comprising a first memory unit and a second memory unit disposed on a sidewall of the first memory unit, the first memory unit, form the substrate up, at least comprising a floating gate suitable for storing a first bit and a first control gate, and the second memory unit, from the substrate up, at least comprising a charge trapping layer suitable for storing a second bit and a second control gate, a first source/drain region and a second source/drain region disposed in the N-type well regions at both sides of the memory cell; the operating method comprising:
 performing a programming operation by applying a first voltage to the first source/drain region, applying a second voltage to the second source/drain region, applying a third voltage to the first control gate, applying a fourth voltage to the second control gate, applying a fifth voltage to the N-type well region, wherein the third voltage is larger than the first voltage, so that the band gap between valance band and conduction band is used to induce a hot-electron injection effect, by which the electrons are injected to the floating gate where a first bit is stored.   
     
     
         2 . The method of  claim 1 , wherein the first voltage is a negative voltage and the third voltage is a positive voltage. 
     
     
         3 . The method of  claim 1 , wherein the first voltage is about −5V, the second voltage is about 0V, the third voltage is about 6V, the fourth voltage is about 0V and the fifth voltage is about 0V. 
     
     
         4 . The method of  claim 1 , further comprising performing a programming operation by applying the first voltage to the first source/drain region, applying the second voltage to the second source/drain region, applying a sixth voltage to the first control gate, applying a seventh voltage to the second control gate and applying the fifth voltage to the N-type well region, wherein the seventh voltage is larger than the first voltage, the first voltage is larger than the sixth voltage, so that the channel hot-holes are used to induce hot-electron injection effect, by which the electrons are injected to the charge trapping layer where a second bit is stored. 
     
     
         5 . The method of  claim 4 , wherein the sixth voltage is about −12V and the seventh voltage is about −1V. 
     
     
         6 . The method of  claim 1 , further comprising performing an erasing operation by applying an eighth voltage to the second source/drain region, applying a ninth voltage to the first control gate, applying a tenth voltage to the second control gate, applying a eleventh voltage to the N-type well region and floating the first source/drain region, wherein the ninth voltage and the tenth voltage are less than the eleventh voltage, so that a FN tunneling effect is used for inducing the electrons stored in the floating gate and the electrons stored in the charge trapping structure into the N-type well region. 
     
     
         7 . The method of  claim 6 , wherein the eighth voltage is about 0V, the ninth voltage is about −15V, the tenth voltage is about −15V and the eleventh voltage is about 0V. 
     
     
         8 . The method of  claim 1 , further comprising performing a reading operation by applying a twelfth voltage to the first source/drain region, applying a thirteenth voltage to the second source/drain region, applying a fourteenth voltage to the first control gate, applying a fifteenth voltage to the second control gate and applying a sixteenth voltage to the N-type well region, wherein the fifteenth voltage is less than the fourteenth voltage and the fourteenth voltage is less than the thirteenth voltage, so as to open a channel below the second memory unit for reading the first bit stored in the floating gate. 
     
     
         9 . The method of  claim 8 , wherein the twelfth voltage is about 0V, the thirteenth voltage is about −1.5V, the fourteenth voltage is about −3V, the fifteenth voltage is about −6V and the sixteenth voltage is about 0V. 
     
     
         10 . The method of  claim 8 , further comprising performing a reading operation by applying the twelfth voltage to the first source/drain region, applying the thirteenth voltage to the second source/drain region, applying a seventeenth voltage to the first control gate, applying an eighteenth voltage to the second control gate and applying the sixteenth voltage to the N-type well region, wherein the seventeenth voltage is less than the eighteenth voltage and the eighteenth voltage is less than the thirteenth voltage, so as to open a channel below the first memory unit for reading the second bit stored in the charge trapping layer. 
     
     
         11 . The method of  claim 10 , wherein the seventeenth voltage is about −6V and the eighteenth voltage is about −3V.