Non-Volatile Memory In CMOS Logic Process

Abstract

A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).

1 . A method of operating a non-volatile memory cell having an access transistor, a control capacitor and a programming transistor having a common floating gate electrode, the method comprising:
 injecting electrons into the floating gate electrode via tunneling through a gate dielectric of the programming transistor by applying positive bias to a diffusion region of the control capacitor.   
     
     
         2 . The method of  claim 1 , further comprising:
 removing electrons from the floating gate electrode via tunneling through the gate dielectric of programming transistor by applying negative bias to the diffusion region of the control capacitor.   
     
     
         3 . The method of  claim 1 , further comprising controlling the charge on the floating gate electrode to define a stored logic state, wherein the charge is controlled by carrier tunneling to and from the floating gate electrode through gate dielectric material of the programming transistor. 
     
     
         4 . The method of  claim 1 , further comprising applying a bias voltage to a source and drain of the programming transistor that is larger than a junction breakdown voltage. 
     
     
         5 . The method of  claim 1 , further comprising:
 removing electrons from the floating gate electrode via tunneling through the gate dielectric of programming transistor by applying a ground bias to the diffusion region of the control capacitor.   
     
     
         6 . The method of  claim 5 , wherein the steps of injecting electrons and removing electrons are implemented using non-negative bias voltages only. 
     
     
         7 . The method of  claim 1 , further comprising performing a read operation by grounding the diffusion region of the control capacitor and sensing a current through the access transistor. 
     
     
         8 . A method of operating a non-volatile memory system comprising,
 providing a non-volatile memory cell fabricated using a conventional logic process and including a control capacitor with a diffusion electrode and a p-channel access device, wherein the control capacitor and the p-channel access device share a floating gate electrode, and wherein a voltage on the floating gate electrode closely tracks a voltage on the diffusion electrode;   reading data stored by the non-volatile memory cell by sensing current flow through the p-channel access device;   maintaining the diffusion electrode of the control capacitor at a ground supply voltage while reading data stored by the non-volatile memory cell.