Logical Operation Circuit and Logical Operation Device

Abstract

To provide a logical operation circuit and a logical operation device which can performs a logical operation using a ferroelectric capacitor. The area ratio between the ferroelectric capacitors CF 1 and CF 2 are set such that the potential difference Vdef between voltages Va 1 and Va 0 is as large as possible, and a transistor MP has a threshold voltage Vth which is about ½·(Va 0 +Va 1 ). Thus, the ON/OFF operation margin of the transistor MP can be significantly large. As a result, a reading process can be performed at a high speed without using an amplifying circuit such as a sense amplifier. Also, the logical operation circuit and the logical operation device can be highly integrated with ease since no sense amplifier is used.

1 . A logical operation circuit comprising:
 a first ferroelectric capacitor which can retain a polarization state corresponding to a specified logical operator and which has first and second terminals;   first and second signal lines which can provide first and second operation target data to the first and second terminals, respectively, of the first ferroelectric capacitor retaining the polarization state corresponding to the specified logical operator and which are connected to the first and second terminals, respectively; and   an operation result output section which, when the residual polarization state of the first ferroelectric capacitor determined by the provision of the two operation target data is either a first residual polarization state or a second residual polarization state having a polarization direction opposite that of the first residual polarization state, outputs the result of a logical operation performed on the first and second operation target data according to the logical operator based on the residual polarization state of the first ferroelectric capacitor, which has a second ferroelectric capacitor having a third terminal connected to the first signal line and a fourth terminal connected to a first reference potential, and which, when outputting the logical operation result, connects the first and second signal lines to the first reference potential and releases the connection, then connects the second signal line to a second reference potential, and outputs the logical operation result based on a potential generated in the first signal line when the second signal line is connected to the second reference potential,   wherein the area ratio Ra of the area of the second ferroelectric capacitor to the area of the first ferroelectric capacitor satisfies the following relation:
   1/(1+ C 0/ C 1· Ra )−1/(1+ Ra )≧0.75(1/(1+√( C 0/ C 1))−1/(1+√( C 1/ C 0))) 
   wherein   C 0 : the first ferroelectric capacitor's average capacitance at the time of non-inversion, and   C 1 : the first ferroelectric capacitor's average capacitance at the time of inversion.   
   
   
       2 - 27 . (canceled)