Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer

Abstract

This invention discloses method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.

1 . A trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein:
 said trenched gate further includes at least two mutually insulated trench-filling segments with an inter-segment insulation layer filling an over-etching pocket along sidewalls of said trenched gate surrounding a top portion of said bottom trench-filling segment thus preventing a top trench-filling segment to extend into said over-etching pocket.   
   
   
       2 . The trenched semiconductor power device of  claim 1  further comprising:
 said inter-segment insulation layer is substantially thicker than a gate insulation layer disposed on trench sidewalls surrounding a top trench-filling segment.   
   
   
       3 . The trenched semiconductor power device of  claim 2  further comprising:
 said inter-segment insulation layer and said gate insulation layer further comprising a continuous high density plasma (HDP) deposition layer   
   
   
       4 . The trenched semiconductor power device of  claim 2  further comprising:
 said inter-segment insulation layer further comprising a HDP deposition layer with an etching rate substantially equal to the etching rate of a thermal oxide.   
   
   
       5 . The trenched semiconductor power device of  claim 2  further comprising:
 said inter-segment insulation layer is a HDP deposition layer processed by an anneal operation at a temperature substantially above a temperature of 800 degrees Celsius.   
   
   
       6 . The trenched semiconductor power device of  claim 2  further comprising:
 said inter-segment insulation layer is a HDP deposition layer processed by an anneal operation followed by an chemistry-mechanical planarization (CMP) and an etch process to provide a planarized surface of said HDP deposition layer.   
   
   
       7 . The trenched semiconductor power device of  claim 2  wherein:
 said trench-filling segments further comprising polysilicon segments.   
   
   
       8 . The trenched semiconductor power device of  claim 7  wherein:
 said top trench-filling segments further comprising polysilicon segments with top surface higher than a top surface of said source region.   
   
   
       9 . The trenched semiconductor power device of  claim 2  wherein:
 said trenched gate further comprising an insulation layer disposed on sidewalls and bottom surface of said trench as an insulating padding layer for said trench-filling segments.   
   
   
       10 . The trenched semiconductor power device of  claim 2  wherein:
 said trenched gate further comprising an insulation layer disposed on sidewalls and bottom surface of said trench as an insulating padding layer for said trench-filling segments wherein said insulation layer disposed on the bottom surface of said trench is substantially thicker than said insulation layer disposed on said sidewalls of said trench.   
   
   
       11 . The trenched semiconductor power device of  claim 1  wherein:
 said trench-filling segment below said inter-segment insulation layer constituting an electrode for electrically connected to said source region of said MOSFET device.   
   
   
       12 . The trenched semiconductor power device of  claim 1  wherein:
 said trenched semiconductor power device constituting a N-channel metal oxide semiconductor field effect transistor (MOSFET) device.   
   
   
       13 . The trenched semiconductor power device of  claim 1  wherein:
 said trenched semiconductor power device constituting a P-channel MOSFET device.   
   
   
       14 . A method for manufacturing a trenched semiconductor power device comprising step of opening a trench in a semiconductor substrate and said method further comprising:
 filling said trench with a trenching filling material followed by an etch back process to remove from a top portion of said trench until a desired depth is reached; and   depositing a high density plasma (HDP) oxide layer followed by an annealing densification process at an elevated temperature for increasing an etch rate of said HDP oxide layer to be substantially the same as an etch rate of a thermal oxide.   
   
   
       15 . The method of  claim 14  wherein:
 said step of annealing densification process further comprising a step of carrying out said annealing densification process in a N2 of O2/N2 ambient environment to carry out a wet oxidation.   
   
   
       16 . The method of  claim 14  wherein:
 said step of annealing densification process further comprising a step of carrying out said annealing densification process in a N2 of O2/N2 ambient environment at a temperature above 850 degrees Celsius for approximately 30 seconds to carry out a RTP process.   
   
   
       17 . The method of  claim 14  wherein:
 said step of annealing densification process further comprising a precisely controlled RTP anneal process whereby said HDP oxide layer having substantially a same etch rate as an etch rate of a thermal oxide.   
   
   
       18 . The method of  claim 14  further comprising:
 dry etching back said HDP oxide layer to expose said HDP oxide layer followed by a dry or wet-etch to obtain a desired HDP oxide layer thickness.   
   
   
       19 . The method of  claim 17  further comprising:
 applying a chemical-mechanical planarization (CMP) process on said HDP oxide layer.   
   
   
       20 . The method of  claim 14  wherein:
 said step of filling said trench with a trench filling material further comprising a step of filling said trench with an un-doped polysilicon then doping said polysilicon with POCL3 followed by implanting phosphorous or boron ions.   
   
   
       21 . The method of  claim 14  wherein:
 said step of etching back to remove said trench filling material from a top portion of said trench further forming an over-etching pocket along sidewalls of said trench near a top portion of a bottom portion of said trench-filling material; and   said step of depositing a high density plasma (HDP) oxide layer further comprising a step of filling said over-etching pocket for improving a device ruggedness of said semiconductor power device.   
   
   
       22 . The method of  claim 14  further comprising:
 filling said trench on top of said inter-segment insulation layer to form at least two mutually insulated trench-filling segments constituting a split gate for said semiconductor device.   
   
   
       23 . The method of  claim 22  further comprising:
 implanting a source region surrounding said split gate and impaling a body region encompassing said source region for manufacturing said semiconductor power device as a trenched metal oxide semiconductor field effect transistor (MOSFET) device.   
   
   
       24 . The method of  claim 14  further comprising:
 growing a thermal oxide layer along a bottom and sidewall of said trench; depositing a HDP oxide layer overlaying said thermal oxide layer; removing oxide layers along trench sidewall; re-growing a thermal oxide layer along said trench sidewall whereas said thermal oxide layer along side trench sidewall is thinner than said HDP oxide layer at said trench bottom.   
   
   
       25 . A method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer separating a top and a bottom gate segments, the method further comprising:
 forming said inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.