Simultaneous Formation of a Top Oxide Layer in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Transistor and a Gate Oxide in a Metal Oxide Semiconductor (MOS)

Abstract

A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide nitride oxide silicon (SONOS) transistor is formed. Additionally, oxide layers are simultaneously formed over the nitride layer corresponding to where at least one SONOS memory transistor is formed and over the exposed silicon substrate corresponding to where at least one metal oxide semiconductor (MOS) transistor is formed.

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       14 . A semiconductor chip comprising:
 a nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory transistor comprising an oxide-nitride-oxide (ONO) structure, wherein said ONO structure comprises a top oxide layer;   at least one metal oxide semiconductor (MOS) transistor corresponding to said SONOS based nonvolatile memory transistor comprising a gate oxide layer, wherein a density of said top oxide layer is substantially similar to a density of said gate oxide layer of said at least one MOS transistor, and wherein a thickness of said gate oxide layer is approximately greater than one and a half times a thickness of said top oxide layer.   
   
   
       15 . The semiconductor chip of  claim 14 , wherein said at least one MOS comprises a first MOS transistor located adjacent said SONOS based nonvolatile memory transistor. 
   
   
       16 . The semiconductor chip of  claim 15 , wherein said at least one MOS comprises a second MOS transistor located adjacent said SONOS based nonvolatile memory transistor such that said SONOS based nonvolatile memory transistor, said first MOS transistor and said second MOS transistor are configured as a tri-gate structure of a nonvolatile memory cell. 
   
   
       17 . The semiconductor chip of  claim 14 , wherein said SONOS based nonvolatile memory transistor is located in a memory array, and said at least one MOS comprises a MOS located peripherally from said memory array. 
   
   
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       19 . The semiconductor chip of  claim 14 , wherein said thickness of said gate oxide layer is approximately twice said thickness of said top oxide layer. 
   
   
       20 . The semiconductor chip of  claim 14 , wherein said thickness of said gate oxide layer is approximately greater than twice said thickness of said top oxide layer. 
   
   
       21 . The semiconductor chip of  claim 14 , wherein said MOS transistor is located adjacent said SONOS memory transistor.