Nonvolatile memory device and methods of fabricating the same

Abstract

A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first conductive layer. The method also includes forming a plurality of floating gates on the insulating layer by etching the first conductive layer using the hard mask pattern as a mask, forming a tunnel insulating layer on the semiconductor substrate including floating gates and the insulating layer, and depositing a second conductive layer on the tunnel insulating layer. The method further includes forming a plurality of control gate electrodes across the active regions by etching the second conductive layer, forming source and drain regions in the semiconductor substrate by performing an ion implantation, and forming contacts in the drain regions.

1 - 10 . (canceled) 
   
   
       11 . A nonvolatile memory device comprising:
 a plurality of active regions on a semiconductor substrate, the active regions being defined by a plurality of device isolation layers;   floating gates positioned on the active regions;   control gate electrodes positioned across the active regions, the control gate electrodes covering an entirety of a top surface and one sidewall of the respective floating gate, the control gate electrodes being extended from one sidewall of each floating gate so as to cover some portion of the active region adjacent to each floating gate;   a tunnel oxide layer positioned between the floating gates and the control gate electrodes on the semiconductor substrate;   a gate insulating layer positioned between the floating gates and the active regions on the semiconductor substrate;   source regions in the semiconductor substrate, the source regions being positioned in the active regions between adjacent floating gates; and   drain regions in the semiconductor substrate, the drain regions being positioned in the active regions between portions of the control gate electrodes which are extended from one sidewall of each floating gate.   
   
   
       12 . The nonvolatile memory device as defined by  claim 11 , wherein the nonvolatile memory device has bilateral symmetry. 
   
   
       13 . The nonvolatile memory device as defined by  claim 11 , wherein sidewall oxide layers are positioned on sidewalls of the floating gates. 
   
   
       14 . The nonvolatile memory device as defined by  claim 13 , wherein nitride spacers is positioned on the sidewalls of the sidewall oxide layers. 
   
   
       15 . The nonvolatile memory device as defined by  claim 14 , wherein the nitride spacers have a height less than that of the sidewall oxide layers. 
   
   
       16 . The nonvolatile memory device as defined by  claim 11 , wherein the control gate electrodes are made of polysilicon or metal polycide. 
   
   
       17 . The nonvolatile memory device as defined by  claim 11 , wherein a drain contact is positioned on each drain region. 
   
   
       18 . The nonvolatile memory device as defined by  claim 11 , wherein the gate insulating layer is extended so that it is positioned between the control gate electrodes and the active regions. 
   
   
       19 . The nonvolatile memory device as defined by  claim 18 , wherein the tunnel oxide layer is extended from the sidewalls of the floating gates so that it is positioned between the control gate electrodes and the gate insulating layer.