Electrostatic discharge protection device and method of fabricating same

Abstract

A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

1 . A method of fabricating a silicon control rectifier, comprising:
 forming a blanket doped region in a silicon layer, a top surface of said silicon layer defining a horizontal plane, an entire bottom surface of said silicon layer in contact with a top surface of a buried oxide layer of a silicon-on-insulator substrate, an entire perimeter of said blanket doped region abutting an insulating layer, said insulating extending from said top surface of said silicon layer to said top surface of said buried oxide layer;   forming a first doped region in said silicon layer, said first doped region dividing said blanket doped region into a second doped region and a third doped region, said first doped region between and abutting said second and third doped regions, said second and third doped regions not abutting, said first, second and third doped regions abutting said insulating layer;   forming a fourth doped region in said second doped region, said fourth doped region abutting only said second doped region and said insulating layer; and   forming a fifth doped region in said third doped region, said fifth doped region abutting only said third doped region and said insulating layer.   
     
     
         2 . The method of  claim 1 , wherein said first doped region has a first net peak doping concentration, said second doped region has a second net peak doping concentration and said third doped region has a third net peak doping concentration, said second and third net peak doping concentrations being a same doping concentration. 
     
     
         3 . The method of  claim 2 , wherein said fourth doped region has a fourth net peak doping concentration and said fifth doped region has a fifth net peak doping concentration. 
     
     
         4 . The method of  claim 1 , wherein said first and fifth doped regions are doped N-type and said second, third and fourth doped regions are doped P-type. 
     
     
         5 . The method of  claim 1 :
 wherein a net peak doping concentration of said fourth doped region is greater than a net peak doping concentration of said first doped region and a net peak doping concentration of said third doped region; and   wherein a net peak doping concentration of said fifth doped region is greater than said net peak doping concentration of said first doped region and said net peak doping concentration of said third doped region.   
     
     
         6 . The method of  claim 1 , wherein a net peak doping concentration of said third doped region is greater than a net peak doping concentration of said first region. 
     
     
         7 . The method of  claim 1 , wherein net peak doping concentrations of said fourth and fifth doped regions are both at least two orders of magnitude greater than net peak doping concentrations of both of said first and third doped regions. 
     
     
         8 . The method of  claim 1 , further including:
 forming a first polysilicon gate over second doped region, said second doped region contained completely under said first polysilicon gate; and   forming a second polysilicon gate over said third doped region, said third doped region contained completely under said second polysilicon gate.   
     
     
         9 . The method of  claim 8 , further including:
 connecting said first gate to said second gate;   connecting said first doped region to a first terminal of a power supply and connecting said fifth doped region to a second terminal of said power supply; and   connecting said fourth doped region to an integrated circuit of said substrate.   
     
     
         10 . The method of  claim 8 , further including:
 forming dielectric spacers on sidewalls of said first and second polysilicon gates; and   forming a silicide layer on top surfaces of said first, fourth and fifth regions where said first, fourth and fifth regions are not protected by said first or second polysilicon gates and said pacers.   
     
     
         11 . The method of  claim 1 , further including:
 adjusting a distance between said second and third doped regions in order to adjust the turn-on speed of said silicon control rectifier.   
     
     
         12 . The method of  claim 1 , further including:
 adjusting a width of said first doped region in order to adjust a current carrying capacity of said silicon control rectifier, said width measured in a direction perpendicular to said distance.   
     
     
         13 . The method of  claim 1 , further including:
 forming a sixth doped region in said silicon layer simultaneously with said forming said fourth doped region, said fourth and sixth doped regions having a same dopant species and net peak doping concentration, said sixth doped region abutting only said third region and said insulating layer.   
     
     
         14 . The method of  claim 1 , further including:
 forming a seventh doped region in said silicon layer simultaneously with said forming said fifth doped region, said fifth and seventh doped regions having a same dopant species and net peak doping concentration, said seventh doped region abutting only said first, second and third doped regions and said insulating layer.   
     
     
         15 . The method of  claim 1 , wherein a path of current flow from said fourth doped region, through said second doped region, said first doped region and said third doped region to said fifth doped region, is in a single horizontal direction parallel to said horizontal plane. 
     
     
         16 . The method of  claim 1 , further including:
 forming a sixth doped region in said silicon layer simultaneously with said forming said fourth doped region, said fourth and sixth doped regions having a same dopant species and net peak doping concentration, said sixth doped region abutting only said third region and said insulating layer; and   forming a seventh doped region in said silicon layer simultaneously with said forming said fifth doped region, said fifth and seventh doped regions having a same dopant species and net peak doping concentration, said seventh doped region abutting only said first, second and third doped regions and said insulating layer.   
     
     
         17 . The method of  claim 16 , further including:
 forming a first polysilicon gate over second doped region, said second doped region contained completely under said first polysilicon gate; and   forming a second polysilicon gate over said third doped region, said third doped region contained completely under said second polysilicon gate.   
     
     
         18 . The method of  claim 17 , further including:
 connecting said first gate to said second gate;   connecting said first doped region through said seventh doped region to a first terminal of a power supply and connecting said fifth doped region through said sixth doped region to a second terminal of said power supply; and   connecting said fourth doped region to an integrated circuit of said substrate.   
     
     
         19 . The method of  claim 17 , further including:
 forming dielectric spacers on sidewalls of said first and second polysilicon gates; and   forming a silicide layer on top surfaces of said first, fourth, fifth, sixth and seventh regions where said first, fourth, fifth and sixth doped regions are not protected by said first or second polysilicon gates and said pacers.   
     
     
         20 . The method of  claim 19 , wherein said first doped region, said third doped region and said fourth doped regions form respectively the base, collector and emitter of a first bipolar transistor and wherein said third doped region, said first doped region and said fifth doped regions form respectively the base, collector and emitter of a second bipolar transistor.