SEMICONDUCTOR DEVICE HAVING PARTIALLY INSULATED FIELD EFFECT TRANSISTOR (PiFET) AND METHOD OF FABRICATING THE SAME

Abstract

Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.

1 . A method of fabricating a semiconductor device comprising:
 sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer to form a semiconductor substrate;   removing the sacrificial layer to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer; and   assembling a transistor on the semiconductor substrate.   
     
     
         2 . The method of  claim 1 , wherein sequentially stacking comprises connecting at least one connection part of the top semiconductor layer to the bottom semiconductor layer through the sacrificial layer. 
     
     
         3 . The method of  claim 2 , wherein the at least one connection part has a pillar shape or a bar shape. 
     
     
         4 . The method of  claim 2 , wherein sequentially stacking comprises:
 epitaxially growing the sacrificial layer on the bottom semiconductor layer;   patterning the sacrificial layer to form at least one opening that exposes a top surface of the bottom semiconductor layer; and   epitaxially growing the top semiconductor layer on the sacrificial layer and within the at least one opening.   
     
     
         5 . The method of  claim 4 , wherein patterning the sacrificial layer comprises patterning the sacrificial layer so that the at least one opening has a circular shape. 
     
     
         6 . The method of  claim 4 , further comprising, before patterning the sacrificial layer, depositing a middle semiconductor layer on the sacrificial layer, wherein the middle semiconductor layer and the top semiconductor layer are composed of the same material. 
     
     
         7 . The method of  claim 1 , wherein sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer comprises:
 providing a semiconductor wafer for the bottom semiconductor layer;   forming a first crystalline semiconductor structure for the sacrificial layer, the first crystalline semiconductor structure capable of being selectively etched with respect to the semiconductor wafer; and   forming a second crystalline semiconductor structure for the top semiconductor layer, the second crystalline semiconductor structure being formed on the first crystalline semiconductor structure using an epitaxial growth process.   
     
     
         8 . The method of  claim 7 , wherein the bottom semiconductor layer comprises a single-crystal silicon layer, the sacrificial layer comprises a silicon germanium layer, and the top semiconductor layer comprises an epitaxial silicon layer. 
     
     
         9 . The method of  claim 1 , wherein removing the sacrificial layer comprises:
 patterning the top semiconductor layer to form a trench that exposes the sacrificial layer in a predetermined region; and   selectively removing the exposed sacrificial layer from the predetermined region.   
     
     
         10 . The method of  claim 9 , further comprising, before assembling the transistor, filling the trench with a field isolation layer. 
     
     
         11 . The method of  claim 10 , wherein filling the trench with a field isolation layer comprises:
 depositing a thermal oxide layer on inner walls of the trench and the buried gap region; and   filling the trench having the thermal oxide with a trench insulation layer.   
     
     
         12 . The method of  claim 11 , wherein filling the trench with the trench insulation layer comprises performing at least one selected from the group consisting of a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, and a spin-on glass (SOG) process. 
     
     
         13 . The method of  claim 11 , wherein filling the trench with a trench insulation layer comprises using a low pressure deposition process so that an inner pressure of the buried gap region is lower than an atmospheric pressure. 
     
     
         14 . The method of  claim 11 , further comprising, before filling the trench with the trench insulation layer, depositing a silicon nitride liner on inner walls of the trench and the buried gap region having the thermal oxide layer. 
     
     
         15 . The method of  claim 10 , wherein filling the trench with the field isolation layer comprises:
 patterning the top semiconductor layer and the sacrificial layer to form a top semiconductor pattern and a sacrificial pattern, respectively, and to form a trench exposing at least the bottom semiconductor layer at a predetermined region;   filling the trench with a first field isolation layer;   patterning the first field isolation layer to form a first field isolation pattern that defines an opening exposing a sidewall of the sacrificial pattern at a predetermined region and supports the top semiconductor pattern at another region;   selectively removing the exposed sacrificial pattern to form the buried gap region; and   filling the opening with a second field isolation pattern,   wherein the field isolation layer is composed of the first field isolation pattern and the second field isolation pattern.   
     
     
         16 . The method of  claim 15 , wherein filling the opening with a second field isolation pattern comprises sealing up or filling the buried gap region. 
     
     
         17 . The method of  claim 10 , wherein filling the trench with the field isolation layer comprises:
 patterning the top semiconductor layer and the sacrificial layer to form first trenches exposing at least the bottom semiconductor layer at a predetermined region;   filling the first trenches with first field isolation patterns;   patterning the top semiconductor layer and the sacrificial layer to form second trenches exposing at least the sacrificial layer and crossing over the first trenches;   selectively removing the exposed sacrificial layer to form the buried gap region; and   filling the second trenches with second field isolation patterns,   wherein the trench is composed of the first trenches and the second trenches and the field isolation layer is composed of the first field isolation patterns and the second field isolation patterns.   
     
     
         18 . The method of  claim 17 , wherein filling the second trenches comprises sealing up or filling the buried gap region. 
     
     
         19 . The method of  claim 1 , further comprising, before forming the transistor, filling at least a part of the buried gap region with a buried insulation layer. 
     
     
         20 . The method of  claim 19 , wherein filling at least part of the buried gap region with a buried insulation layer comprises filling at least part of the buried gap region with one chosen from the group consisting of a silicon thermal oxide layer, a silicon nitride layer, and a CVD oxide layer. 
     
     
         21 . A method of forming a semiconductor device, comprising:
 disposing a sacrificial layer on a silicon substrate, the sacrificial layer having at least one opening that exposes a predetermined region of the silicon substrate;   filling the at least one opening with an epitaxial silicon layer that covers a surface of the silicon substrate including the sacrificial layer;   patterning the epitaxial silicon layer to form a trench that exposes the sacrificial layer;   selectively removing the exposed sacrificial layer to form a buried gap region between the epitaxial silicon layer and the silicon substrate;   filling the trench with an insulation layer;   disposing source/drain regions in the epitaxial silicon layer; and   disposing a gate electrode over the epitaxial silicon layer.   
     
     
         22 . The method of  claim 21 , wherein filling the trench with the insulation layer comprises filling at least a part of the buried gap region. 
     
     
         23 . The method of  claim 21 , wherein filling at least a part of the buried gap region filling at least part of the buried gap region with at least selected from the group consisting of a silicon thermal oxide layer, a silicon nitride layer, and a CVD silicon oxide layer.