Memory Module Including A Plurality Of Integrated Circuit Memory Devices And A Plurality Of Buffer Devices In A Matrix Topology

Abstract

A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a plurality of portions of the memory module data bus that is coupled to the respective integrated circuit buffer devices. Each integrated circuit buffer device is also coupled to a bus that provides control information that specifies an access to at least one integrated circuit memory devices. According to an embodiment, a SPD device stores information regarding configuration information of the memory module. In embodiments, at least one integrated circuit buffer devices access information stored in the SPD device. In a package embodiment, a package houses an integrated circuit buffer die and a plurality of integrated circuit memory dies.

1 . A memory module comprising:
 an integrated circuit memory device; and   an integrated circuit buffer device coupled to the integrated circuit memory device, wherein a memory access to the integrated circuit memory device is performed via the integrated circuit buffer device, the integrated circuit buffer device including a storage circuit to store redundancy information pertaining to a defective memory cell of the integrated circuit memory device such that the integrated circuit buffer device reroutes a memory access having an address associated with the defective memory cell.   
     
     
         2 . The memory module of  claim 1 , wherein the integrated circuit buffer device reroutes the memory access having the address associated with the defective memory cell to another integrated circuit memory device. 
     
     
         3 . The memory module of  claim 1 , wherein the integrated circuit buffer device reroutes the memory access having the address associated with the defective memory cell to another address of the integrated circuit memory device. 
     
     
         4 . The memory module of  claim 1 , wherein a first plurality of values is written to the address and then a second plurality of values is read from the address to detect the defective memory cell, wherein the defective memory cell is detected when the first plurality of values does not match the second plurality of values. 
     
     
         5 . The memory module of  claim 1 , wherein the integrated circuit memory device and integrated circuit buffer device are included in a single common package. 
     
     
         6 . A memory module comprising:
 a plurality of integrated circuit memory devices, each integrated circuit memory device of the plurality of integrated circuit memory devices having an array of memory cells; and   an integrated circuit buffer device coupled to the plurality of integrated circuit memory devices, wherein a memory access to the plurality of integrated circuit memory devices is performed via the integrated circuit buffer device, the integrated circuit buffer device including a storage circuit to store information pertaining to at least one defective memory cell location of at least one array of memory cells.   
     
     
         7 . The memory module of  claim 6 , wherein a first plurality of values is written to an address of an integrated circuit memory device in the plurality of integrated circuit memory devices and then a second plurality of values is read from the address of the integrated circuit memory device to detect the at least one defective memory cell location, wherein the defective memory cell location is detected when the first plurality of values does not match the second plurality of values. 
     
     
         8 . The memory module of  claim 7 , wherein, during initialization of the plurality of integrated circuit memory devices, both the first plurality of values is written and the second plurality of values is read. 
     
     
         9 . The memory module of  claim 6 , wherein the integrated circuit buffer device is included in a plurality of integrated circuit buffer devices, each integrated circuit buffer devices of the plurality of integrated circuit buffer devices coupled to a corresponding plurality of integrated circuit memory devices, wherein a memory access to each plurality of integrated circuit memory devices is performed via a corresponding integrated circuit buffer device in the plurality of integrated circuit buffer devices. 
     
     
         10 . The memory module of  claim 9 , further comprising a bus coupled to the plurality of integrated circuit buffer devices, the bus to provide control information associated with the memory access to the plurality of integrated circuit buffer devices. 
     
     
         11 . A memory module comprising:
 a plurality of integrated circuit memory devices, each integrated circuit memory device of the plurality of integrated circuit memory devices having an array of memory cells;   an integrated circuit buffer device coupled to the plurality of integrated circuit memory devices, wherein a memory access to the plurality of integrated circuit memory devices is performed via the integrated circuit buffer device; and   an integrated circuit storage device coupled to the integrated circuit buffer device, the integrated circuit storage device to store information pertaining to at least one defective memory cell location of at least one array of memory cells of the plurality of integrated circuit memory devices.   
     
     
         12 . The memory module of  claim 11 , when the information pertaining to at least one defective cell location is obtained during initialization of the memory module. 
     
     
         13 . The memory module of  claim 11 , wherein a first plurality of values is written to an address of an integrated circuit memory device in the plurality of integrated circuit memory devices and then a second plurality of values is read from the address of the integrated circuit memory device to detect the at least one defective memory cell location, wherein the defective memory cell location is detected when the first plurality of values does not match the second plurality of values. 
     
     
         14 . The memory module of  claim 11 , wherein the array of memory cells include dynamic random access memory cells. 
     
     
         15 . The memory module of  claim 11 , wherein the integrated circuit buffer device reroutes a memory access having an address associated with the defective memory cell location to another address in the plurality of integrated circuit memory devices. 
     
     
         16 . A system housed in a single semiconductor package, the system comprising:
 a first integrated circuit memory die having an array of memory cells; and   a integrated circuit buffer die coupled to the integrated circuit memory die, wherein a memory access to the integrated circuit memory die is performed via the integrated circuit buffer die, the integrated circuit buffer die including a storage circuit to store information pertaining to at least one defective memory cell location in the array of memory cells.   
     
     
         17 . The system of  claim 16 , wherein the array of memory cells includes dynamic random access memory cells. 
     
     
         18 . The system of  claim 17 , wherein the storage circuit is a register. 
     
     
         19 . The system of  claim 16 , wherein the integrated circuit buffer die reroutes the memory access to another memory location in the array of memory cells in response to the information pertaining to at least one defective memory cell location. 
     
     
         20 . The system of  claim 16 , further comprising a second integrated circuit memory die having an array of memory cells, wherein the integrated circuit buffer die reroutes the memory access to array of memory cells of the second integrated circuit memory die in response to the information pertaining to the at least one defective memory cell location. 
     
     
         21 . A system comprising:
 a plurality of integrated circuit memory devices, each integrated circuit memory device of the plurality of integrated circuit memory devices having an array of memory cells; and   a plurality of integrated circuit buffer devices coupled to the plurality of integrated circuit memory devices, wherein a memory access to an integrated circuit memory device of the plurality of integrated circuit memory devices is performed via a corresponding integrated circuit buffer device of the plurality of integrated circuit buffer devices, the corresponding integrated circuit buffer device including a storage circuit to store information pertaining to at least one defective memory cell location of at least one array of memory cells.   
     
     
         22 . The system of  claim 21 , wherein the corresponding integrated circuit buffer device accesses a first set of integrated circuit memory devices in the plurality of integrated circuit memory devices. 
     
     
         23 . The system of  claim 21 , further comprising a bus coupled to the plurality of integrated circuit buffer devices, the bus to provide control information associated with the memory access to the plurality of integrated circuit buffer devices. 
     
     
         24 . The system of  claim 21 , wherein the storage circuit includes a register to store the information pertaining to at the least one defective memory cell location. 
     
     
         25 . The system of  claim 21 , wherein the corresponding integrated circuit buffer device reroutes the memory access to another memory location in the at least one array of memory cells in response to the information pertaining to the at least one defective memory cell location.