Bit line pre-settlement circuit and method for flash memory sensing scheme

Abstract

A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.

1 . A flash memory bit line pre-settlement circuit, including:
 at least one flash memory cell that draws an erased current when in an erased state and a programmed current when in a programmed state;   a cell bit line coupled to the at least one flash cell;   a reference bit line drawing a reference current selected to be about midway between the erased current and the programmed current of the at least one flash memory cell;   a cell current-to-voltage converter coupled to the cell bit line;   a reference current-to-voltage converter coupled to the reference bit line; and   a cell bit line precharge circuit selectively coupling a reference output voltage from the reference current-to-voltage converter to the cell bit line during a bit line precharge period.