Nonvolatile semiconductor memory device

Abstract

In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

1 - 2 . (canceled) 
   
   
       3 . A nonvolatile semiconductor memory device comprising:
 a memory cell including an electric charge accumulation region for storing information in an electric charge form, a first conductive layer formed on said electric charge accumulation region, and a second conductive layer formed above said first conductive layer in alignment with said first conductive layer;   a first voltage setting circuit for setting a voltage of said first conductive layer; and   a second voltage setting circuit for setting a voltage of said second conductive layer, individually and separately from voltage setting of said first conductive layer.   
   
   
       4 . The nonvolatile semiconductor memory device according to  claim 3 , wherein said electric charge accumulation region is comprised of a conductive layer formed into an electrically floating state. 
   
   
       5 . The nonvolatile semiconductor memory device according to  claim 3 , wherein said electric charge accumulation region is comprised of an insulating film. 
   
   
       6 . (canceled)