Thin passivation layer on 3D devices

Abstract

Embodiments of the invention include a device with stacked substrates. Conducting interconnecting structures of one substrate are bonded to conducting interconnecting structures of another substrate. A passivating layer may be on the conducting interconnecting structures between the substrates and may be formed by an atomic layer deposition process or a with a Langmuir-Blodgett technique.

1 . A device, comprising:
 a first semiconductor substrate with conductive interconnecting structures, the conductive interconnecting structures having side walls extending away from the first semiconductor substrate;   a second semiconductor substrate with conductive interconnecting structures, the conductive interconnecting structures having side walls extending away from the second semiconductor substrate, the conductive interconnecting structures of the second semiconductor substrate being bonded to the conductive interconnecting structures of the first semiconductor substrate; and   a first passivating layer on the side walls of the conductive interconnecting structures of the first semiconductor substrate, the passivating layer including a first material with molecules having a polar group at an end close to a surface of the conductive interconnecting structures, an organic chain attached to the polar group and extending away from the surface of the conductive interconnecting structures, and a non-polar group attached to the organic chain.   
   
   
       2 . The device of  claim 1 , wherein the first passivating layer is formed by a Langmuir-Blodgett technique. 
   
   
       3 . The device of  claim 2 , wherein the first passivating layer substantially consists of a monolayer of molecules. 
   
   
       4 . The device of  claim 1 , wherein a second material substantially the same as the first material is located in a bonded region of the bonded conductive interconnecting structures. 
   
   
       5 . The device of  claim 1 , wherein the first and second semiconductor substrates and the passivating layer comprise a stacked integrated circuit attached to a motherboard, and further comprising a graphics processing unit integrated with the motherboard. 
   
   
       6 . The device of  claim 1 , further comprising a second passivating layer on the side walls of the conductive interconnecting structures of the second semiconductor substrate, the second passivating layer comprising a non-organic insulating material different than the first material. 
   
   
       7 . The device of  claim 6 , wherein a fourth material substantially the same as the third material is located in a bonded region of the bonded conductive interconnecting structures. 
   
   
       8 . A device, comprising:
 a first semiconductor substrate with conductive interconnecting structures, the conductive interconnecting structures having side walls extending away from the first semiconductor substrate;   a second semiconductor substrate with conductive interconnecting structures, the conductive interconnecting structures having side walls extending away from the second semiconductor substrate, the conductive interconnecting structures of the second semiconductor substrate being bonded to the conductive interconnecting structures of the first semiconductor substrate;   a first passivating layer on the side walls of the conductive interconnecting structures of the first semiconductor substrate, the first passivating layer comprising a first insulating material; and   wherein a second material substantially the same as the first material is located in a bonded region of the bonded conductive interconnecting structures.   
   
   
       9 . The device of  claim 8 , wherein the first and second semiconductor substrates and the first passivating layer comprise a stacked integrated circuit attached to a motherboard, and further comprising a graphics processing unit integrated with the motherboard. 
   
   
       10 . The device of  claim 8 , wherein the first passivating layer has a thickness less than about 30 angstroms. 
   
   
       11 . The device of  claim 8 , wherein the first passivating layer comprises at least one of aluminum oxide, silicon nitride, or aluminum nitride. 
   
   
       12 . The device of  claim 8 , further comprising a second passivating layer on the side walls of the conductive interconnecting structures of the second semiconductor substrate, the second passivating layer comprising a third material with molecules having a polar group at an end close to a surface of the conductive interconnecting structures, an organic chain attached to the polar group and extending away from the surface of the conductive interconnecting structures, and a non-polar group attached to the organic chain. 
   
   
       13 . The device of  claim 12 , wherein a fourth material substantially the same as the third material is located in a bonded region of the bonded conductive interconnecting structures.