Ultra dense trench-gated power device with reduced drain source feedback capacitance and miller charge

Abstract

The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

1 . A method for forming a semiconductor device with reduced Miller capacitance comprising the steps of:
 heavily doping a substrate with a first conductivity dopant to form a drain region;   growing an epitaxial layer on the substrate and lightly doping the epitaxial layer with a dopant of the first conductivity;   implanting the surface of the epitaxial layer with dopants of a second polarity opposite in polarity to the first conductivity dopant;   covering the substrate with a trench mask having openings corresponding to desired trench regions and removing material from the exposed regions to form trenches;   growing an oxide layer on the trench walls and floor and diffusing the second conductivity dopant to form well regions adjacent the trench sidewalls;   forming over said oxide layer on said trench walls and floor upper and lower conductive layers respectively and separating the layers with a first dielectric layer;   forming source regions on the surface of the epitaxial layer with dopant of the first conductivity; and   connecting the source metal regions to the lower conductive trench layers at locations proximate the periphery of the semiconductor device.   
   
   
       2 . The method of  claim 1  wherein the oxide layer on the trench walls and floor are of a substantially constant thickness. 
   
   
       3 . The method of  claim 1  further comprising the step of removing a portion of said upper conductive layer 
   
   
       4 . A semiconductor device having improved and reduced Miller capacitance in a repeated cellular structure, wherein the cells of the device comprise:
 a substrate having one surface with a first layer highly doped with a first conductivity dopant and forming a drain,   a second layer over the first layer and lightly doped with a first conductivity dopant,   a third layer over the second layer and doped with a second conductivity dopant opposite in polarity to the first conductivity component, and forming a PN junction with the second layer,   a fourth layer on the opposite surface of the semiconductor substrate and highly doped with a first conductivity dopant;   a trench structure extending from the fourth layer into the substrate and dividing the fourth layer into a plurality of source regions,   said trench having spaced apart sidewalls and a floor with an insulating layer having substantially uniform thickness on the sidewalls and floor, upper and lower conductive layers separated by a dielectric layer, and   wherein a floor portion of the trench is disposed below the lower level of the third layer and said floor portion is rounded such that the concentration of electromagnetic field at the bottom of the trench is less than the concentration of electromagnetic field at the bottom of a trench with a substantially flat floor.