Semiconductor device structure with active regions having different surface directions

Abstract

Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.

1 . A semiconductor device structure comprising:
 at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and   wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.   
   
   
       2 . The structure of  claim 1 , wherein the pFETs are located in an active region with a current flow in a <110> surface direction, and the nFETs are located in an active region with a current flow in a <100> surface direction. 
   
   
       3 . The structure of  claim 1 , wherein the pFETs are located in an active region with a (110) surface orientation and a <111> surface direction, and the nFETs are located in an active region with a (100) surface orientation and a <110> surface direction. 
   
   
       4 . The structure of  claim 1 , further comprising means for applying:
 a compressive stress in a longitudinal direction with respect to a current flow of the pFET and a transverse direction with respect to a current flow of the nFET; and   a tensile stress in a longitudinal direction with respect to a current flow of the nFET and a transverse direction with respect to a current flow of the pFET.