Interconnects for semiconductor light emitting devices

Abstract

A semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region and contacts electrically connected to the n-type region and the p-type region is connected to a mount. A metal layer arbitrarily patterned to cover at least 20% of the area of the semiconductor light emitting device is plated on either a metal layer formed on the mount or a metal layer formed on one of the contacts. The plated metal layer may replace other known interconnecting techniques such as stud bumps. The semiconductor light emitting device is physically connected to the mount by causing interdiffusion between the contact surfaces of the metal layers. In some embodiments, a layer of solder is formed over the plated metal layer, and then the semiconductor light emitting device is physically connected to the mount by heating the solder.

1 . A structure comprising a semiconductor light emitting device connected to a mount by at least one interconnect, wherein:
 a total lateral extent of all interconnects is at least 20% of an area of the semiconductor light emitting device; and   the interconnect is one of Au and Cu.   
     
     
         2 . The structure of  claim 1  wherein:
 the semiconductor light emitting device comprises:
 a III-nitride light emitting layer disposed between an n-type region and a p-type region; 
 contacts electrically connected to the n-type region and the p-type region; and 
 a first metal layer formed on one of the contacts; 
   the mount comprises a second metal layer; and   the at least one interconnect is disposed between the first metal layer and the second metal layer.   
     
     
         3 . The structure of  claim 2  wherein:
 the contacts electrically connected to the n-type region and the p-type region are both formed on a bottom side of the device; and   light from the light emitting layer escapes the device through a top side of the device.   
     
     
         4 . The structure of  claim 2  wherein a thickness of the at least one interconnect is between 1 and 50 microns. 
     
     
         5 . The structure of  claim 2  wherein a thickness of the at least one interconnect is between 5 and 20 microns. 
     
     
         6 . The structure of  claim 2  wherein the total lateral extent of all interconnects is at least 30% of an area of the semiconductor light emitting device. 
     
     
         7 . The structure of  claim 2  wherein the total lateral extent of all interconnects is at least 40% of an area of the semiconductor light emitting device.