Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout

Abstract

An apparatus and program product automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.

1 . An apparatus, comprising:
 a processor; and   program code configured to execute on the processor to annotate a functional definition of a circuit design by automatically modifying the functional definition of the circuit design to incorporate a plurality of assignments into the functional definition of the circuit design, wherein the plurality of assignments are generated using a physical definition of the circuit design that has been generated from the functional definition, and wherein the plurality of assignments define connections between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design;   
     wherein the plurality of assignments includes a first assignment configured to couple a first circuit element among the plurality of circuit elements to a first signal among the plurality of signals, wherein the first circuit element is defined in a first HDL file among a plurality of HDL files in the functional definition, and wherein the program code is configured to modify the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition by, for at least the first assignment:
 storing a record associated with the first assignment in a first data structure associated with the first HDL file, wherein the first data structure is among a plurality of data structures respectively associated with the plurality of HDL files; 
 associating a stage identifier with the record in the first data structure, wherein the stage identifier identifies an initial execution stage among a plurality of execution stages; 
 processing the record by retrieving the record from the first data structure and passing the record to the execution stage among the plurality of execution stages that is identified by the stage identifier for the record; and 
 after processing the record, and until the stage identifier for the record indicates that the record has been processed by all of the execution stages, repeatedly:
 incrementing the stage identifier for the record to identify a next execution stage among the plurality of execution stages; 
 storing the record back in the first data structure; and 
 repeating processing of the record by retrieving the record from the first data structure and passing the record to the execution stage among the plurality of execution stages that is identified by the stage identifier for the record. 
 
 
   
   
       2 . The apparatus of  claim 1 , wherein a first circuit element among the plurality of circuit elements includes a latch configured for use in a scan chain, wherein at least one assignment comprises a clock control signal assignment configured to connect the first circuit element to an endpoint among a plurality of endpoints of a distribution tree for a clock control signal, wherein the plurality of assignments are defined in an assignment file, and wherein the program code is configured to automatically modify the functional definition of the circuit design to incorporate the plurality of assignments by:
 locating an instantiation of the first circuit element in a Hardware Description Language (HDL) representation of the functional definition;   retrieving the clock control signal assignment for the first circuit element from the assignment file; and   modifying the HDL representation to connect the circuit element to the endpoint in the distribution tree identified by the clock control signal assignment.   
   
   
       3 . The apparatus of  claim 1 , wherein a first circuit element among the plurality of circuit elements includes a latch configured for use in a scan chain, wherein at least one assignment comprises a scan chain assignment that connects the first circuit element to one of a plurality of scan chains, wherein the plurality of assignments are defined in an assignment file, and wherein the program code is configured to automatically modify the functional definition of the circuit design to incorporate the plurality of assignments by:
 locating an instantiation of the first circuit element in a Hardware Description Language (HDL) representation of the functional definition; and   modifying the instantiation of the first circuit element in the HDL representation to add scan in and scan out port connections for the first circuit element based upon the scan chain assignment.   
   
   
       4 . The apparatus of  claim 3 , wherein the HDL representation of the functional definition includes a plurality of HDL files, wherein the latch is defined in a first HDL file among the plurality of HDL files, and wherein the program code is configured to automatically modify the functional definition of the circuit design to incorporate the plurality of assignments further by:
 adding a port for the first circuit element for each new port connection added when modifying the instantiation of the first circuit element to a data structure that is associated with the first HDL file; and   processing each HDL file among the plurality of files that has been modified to remove any old port connections and add any new port connections identified in the data structure associated with each such HDL file.   
   
   
       5 . A program product, comprising:
 program code configured to annotate a functional definition of a circuit design by automatically modifying the functional definition of the circuit design to incorporate a plurality of assignments into the functional definition of the circuit design, wherein the plurality of assignments are generated using a physical definition of the circuit design that has been generated from the functional definition, and wherein the plurality of assignments define connections between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design; and   a computer readable medium bearing the program code;   
     wherein the plurality of assignments includes a first assignment configured to couple a first circuit element among the plurality of circuit elements to a first signal among the plurality of signals, wherein the first circuit element is defined in a first HDL file among a plurality of HDL files in the functional definition, and wherein the program code is configured to modify the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition by, for at least the first assignment:
 storing a record associated with the first assignment in a first data structure associated with the first HDL file, wherein the first data structure is among a plurality of data structures respectively associated with the plurality of HDL files; 
 associating a stage identifier with the record in the first data structure, wherein the stage identifier identifies an initial execution stage among a plurality of execution stages; 
 processing the record by retrieving the record from the first data structure and passing the record to the execution stage among the plurality of execution stages that is identified by the stage identifier for the record; and 
 after processing the record, and until the stage identifier for the record indicates that the record has been processed by all of the execution stages, repeatedly:
 incrementing the stage identifier for the record to identify a next execution stage among the plurality of execution stages; 
 storing the record back in the first data structure; and 
 repeating processing of the record by retrieving the record from the first data structure and passing the record to the execution stage among the plurality of execution stages that is identified by the stage identifier for the record.