Semiconductor integrated circuit and method of designing the same

Abstract

In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

1 - 4 . (canceled) 
   
   
       5 . A semiconductor integrated circuit designed in a cell-based scheme, comprising:
 a plurality of cells placed so as to be aligned at the top in a plurality of strip areas provided in parallel with each other; and   a plurality of wirings connecting among the cells, wherein   the cells include cells on a clock path and a cell for performing a logical operation, and a cell-placement prohibiting area is set for each of all or part of the cells on the clock path so as to center on the cell on the clock path,   the cell for performing the logical operation is placed in a portion of the strip areas except the cell-placement prohibiting areas, and   a capacitive cell is placed in at least one of the cell-placement prohibiting areas.   
   
   
       6 . The semiconductor integrated circuit according to  claim 5 , wherein
 a cell-placement prohibiting area placed so as to center on a cell in an n-th strip area forms an overlapping area with an (n−1)-th strip area and an (n+1)-th strip area, and   the capacitive cell is placed in the overlapping area.   
   
   
       7 . A method of designing a semiconductor integrated circuit in a cell-based scheme, comprising the steps of:
 placing, in a plurality of strip areas provided in parallel with each other, all or part of cells on a clock path that are among cells included in a circuit to be designed so that the cells on the clock path are aligned at top;   virtually placing, at a position of each cell, a dummy cell which is larger than each cell; and   placing cells not yet placed, which are among the cells included in the circuit to be designed, in a portion of the strip areas except areas where the dummy cells are placed so that the cells not yet placed are aligned at top.   
   
   
       8 . The semiconductor-integrated-circuit designing method according to  claim 7 , wherein
 in the step of placing the cells on the clock path, for all or part of cell groups formed of a plurality of cells on the clock path, cells included in each cell group are closely placed in a single strip area, and   in the step of placing the dummy cell, a dummy cell which is larger than each cell group is virtually set for each cell group.   
   
   
       9 . A method of designing a semiconductor integrated circuit in a cell-based scheme, comprising the steps of:
 placing cells included in a circuit to be designed in a plurality of strip areas provided in parallel with each other so as to be aligned at top;   placing, for each of all or part of cells on a clock path which are among the cells, a cell-placement prohibiting area larger than each cell, at a position of each cell; and   re-placing a cell for performing a logical operation placed in the cell-placement prohibiting area so as to be placed in a portion of the strip areas except the cell-placement prohibiting areas.   
   
   
       10 . The semiconductor-integrated-circuit designing method according to  claim 9 , wherein
 in the step of placing the cells, cells included in cell groups formed of a plurality of cells are closely placed together in a single strip area, and   in the step of setting the cell-placement prohibiting area, the cell-placement prohibiting area is placed for each of all or part of the cell groups on the clock path.   
   
   
       11 - 12 . (canceled) 
   
   
       13 . A method of designing a semiconductor integrated circuit in a cell-based scheme, comprising the steps of:
 placing cells included in a circuit to be designed;   calculating, for each of all or part of cells on a clock path which are among the cells, a degree of drop in a power-supply voltage at each cell occurring due to resistance of a power-supply wiring when a predetermined power-supply voltage is supplied to the circuit to be designed; and   re-placing a cell on a clock path whose degree calculated in the degree calculating step does not satisfy a predetermined reference so that a cell near the cell on the clock path is away from the cell on the clock path.   
   
   
       14 . A semiconductor integrated circuit designed in a cell-based scheme, comprising:
 a plurality of cells placed in a plurality of strip areas provided in parallel with each other so as to be aligned at top;   a first power-supply wiring for supplying power to all or part of cells on a clock path which are among the plurality of cells; and   a second power-supply wiring for supplying power to remaining cells among the plurality of cells, wherein   the first power-supply wiring is provided separately from the second power-supply wiring.   
   
   
       15 . A semiconductor integrated circuit designed in a cell-based scheme, comprising:
 a plurality of cells placed in a two-dimensional area;   a power-supply wiring provided in the two-dimensional area for supplying power to the cells;   an additional power-supply wiring provided in the two-dimensional area separately from the power-supply wiring and applied with a voltage higher than a voltage of the power-supply wiring; and   a voltage converting section for dropping the voltage on the additional power-supply wiring to a power-supply voltage to be supplied to the plurality of cells and applying the dropped voltage to the power-supply wiring.   
   
   
       16 . The semiconductor integrated circuit according to  claim 15 , wherein
 the voltage converting section includes a power transistor.   
   
   
       17 . A semiconductor integrated circuit designed in a cell-based scheme, comprising:
 a plurality of cells placed so as to be aligned at the top in a plurality of strip areas provided in parallel with each other; and   a plurality of wirings connecting among the cells, wherein   a blank area is located around a plurality of cells, on a clock path, placed next to each other.   
   
   
       18 . A semiconductor integrated circuit designed in a cell-based scheme, comprising:
 a plurality of cells placed so as to be aligned at the top in a plurality of strip areas provided in parallel with each other; and   a plurality of wirings connecting among the cells, wherein   a capacitive cell is located around a plurality of cells, on a clock path, placed next to each other.