core circuit test architecture

Abstract

A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

1 . An integrated circuit core comprising:
 A. functional core circuitry having functional flip-flops;   B. a serial scan path that includes the functional flip-flops, the scan path having a stimulus data input, a response data output, and connections between the scan path and functional core circuitry communicating test patterns to and from the functional core circuitry; and   C. compare circuitry having an input connected to the response data output, an expected data input, a mask data input, a fail flag output, a scan path input, and a scan path output.   
   
   
       2 . An integrated circuit comprising:
 A. comparator logic having a response data input connected to the output of a scan path, an expected data input, and an output;   B. mask logic having a mask input, an input connected to the output of the comparator logic, and an output;   C. a fail latch having a logic input connected to the output of the mask logic, a strobe input, and an output;   D. a scan cell having an input connected to the output of the fail latch, a scan input, a scan output, and a control input, the scan cell including a flip-flop and multiplexer combination providing for the capturing of data at its inputs and shifting of the captured data to its output; and   E. buffer circuitry having an input connected to the output of the fail latch and an open drain, fail flag output.   
   
   
       3 . An integrated circuit comprising:
 A. a substrate of semiconductor material;   B. functional core circuitry formed on the substrate, the functional core circuitry including functional flip-flops;   C. a stimulus input lead;   D. first and second scan paths formed on the substrate, each scan path having a stimulus input, connections with the functional core circuitry for communicating test patterns to and from the functional core circuitry, and a response output, each scan path including functional flip-flops of the functional core circuitry that, in a test mode, are connected in series, and the stimulus input of the first scan path being coupled to the stimulus input lead;   E. multiplexer circuitry having a first input coupled to the stimulus input lead, a second input connected to the response output of the first scan path, a control input, and an output connected to the stimulus input of the second scan path; and   F. control circuitry coupled to the scan paths and to the control input of the multiplexer circuitry, the control circuitry including a control bus input.   
   
   
       4 . An integrated circuit comprising:
 A. a substrate of semiconductor material;   B. functional core circuitry formed on the substrate, the functional core circuitry including functional flip-flops;   C. a stimulus input lead;   D. plural scan paths formed on the substrate, each scan path having a stimulus input, connections with the functional core circuitry for communicating test patterns to and from the functional core circuitry, and a response output, each scan path including functional flip-flops of the functional core circuitry that, in a test mode, are connected in series, and the stimulus input of each scan path being coupled to the stimulus input lead;   E. control circuitry coupled to the scan paths, the control circuitry including a control bus input and a high power/low power signal input.   
   
   
       5 . A process of testing an integrated circuit, comprising:
 A. applying an enable signal to control circuitry to provide for the control circuitry to operate scan paths coupled to functional circuitry, including applying an enable signal of one logic state to provide for the control circuitry to operate the scan paths in series between a stimulus input and a response output in a high power mode, and applying an enable signal of another logic state to provide for the control circuitry to operate each scan path separately between the stimulus input and the response output in a low power mode; and   B. applying control signals to the control circuitry to operate the scan paths by shifting test stimulus data from the stimulus input into the scan paths, applying the stimulus data to the combinational logic from each scan path, receiving response data from the combinational logic in each scan path, and shifting test response data from the scan paths to the response output.   
   
   
       6 . A process of testing an integrated circuit comprising:
 A. placing all of the functional core circuits on the integrated circuit in a test mode;   B. simultaneously inputting the same test pattern to all of the plural functional core circuits on one set of parallel test input bus leads connected to test inputs of each functional core circuit; and   C. monitoring a fail flag output lead connected to a fail flag output of each functional core circuit.   
   
   
       7 . An integrated circuit comprising:
 A. plural, identical, functional core circuitry, each including a parallel test input bus, a serial scan path, and a fail flag output;   B. test input bus leads connecting the parallel test input buses together, the test input bus leads being connected to externally accessible test input terminals;   C. serial leads connecting the serial scan paths together in a serial scan path between an externally accessible scan input terminal and an externally accessible scan output terminal; and   D. fail flag leads connecting the fail flag outputs to an externally accessible fail flag terminal.   
   
   
       8 . An integrated circuit comprising:
 A. first functional core circuitry including a parallel test input bus, a serial scan path, and a fail flag output;   B. second functional core circuitry different from the first functional core circuitry, the second functional core circuitry including a parallel test input bus, a serial scan path, and a fail flag output;   C. first test input bus leads connected between the parallel test input bus of the first functional core circuitry and externally accessible first test input terminals;   D. second test input bus leads separate from the first test input bus leads, the second test input bus leads being connected between the parallel test input bus of the second functional core circuitry and externally accessible second test input terminals;   E. serial leads connecting the serial scan paths together in a serial scan path between an externally accessible scan input terminal and an externally accessible scan output terminal; and   F. fail flag leads connecting the fail flag outputs to an externally accessible fail flag terminal.   
   
   
       9 . A semiconductor wafer comprising:
 A. plural, identical, integrated circuit dies, each including a parallel test input bus, a serial scan path, and a fail flag output;   B. test input bus leads connecting the parallel test input buses together, the test input bus leads being connected to externally accessible test input terminals;   C. serial leads connecting the serial scan paths together in a serial scan path between an externally accessible scan input terminal and an externally accessible scan output terminal; and   D. fail flag leads connecting the fail flag outputs to an externally accessible fail flag terminal.   
   
   
       10 . A semiconductor wafer comprising:
 A. plural, identical, integrated circuit dies, each including a first test input bus, a second test input bus, a serial scan path, and a fail flag output;   C. first test input bus leads connected between the first test input bus of all of the integrated circuit dies and externally accessible first test input terminals;   D. second test input bus leads separate from the first test input bus leads, the second test input bus leads being connected between the second test input bus of all of the integrated circuit dies and externally accessible second test input terminals;   E. serial leads connecting the serial scan paths together in a serial scan path between an externally accessible scan input terminal and an externally accessible scan output terminal; and   F. fail flag leads connecting the fail flag outputs to an externally accessible fail flag terminal.