Boolean Processor

Abstract

A processor including a Boolean logic unit, wherein the Boolean logic unit is operable for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, a plurality of input/output interfaces, wherein the plurality of input/output interfaces are operable for receiving a plurality of compiled Boolean expressions/operations and transmitting a plurality of compiled results, and a plurality of registers. An associated processing method including starting an operation related to a Conjunctive Normal Form Boolean expression, wherein the Boolean expression comprises a conjunct, evaluating the conjunct, and selectively short-circuiting a portion of the Boolean expression.

1 . A processing method, comprising:
 starting an operation related to a Conjunctive Normal Form Boolean expression, wherein the Boolean expression comprises a conjunct;   evaluating the conjunct; and   selectively short-circuiting a portion of the Boolean expression.   
   
   
       2 . The processing method of  claim 1 , wherein the conjunct is a stand-alone term evaluated as an AND operation. 
   
   
       3 . The processing method of  claim 1 , wherein the conjunct comprises an OR clause. 
   
   
       4 . The processing method of  claim 3 , wherein each of a plurality of terms of the conjunct is evaluated as part of an OR operation. 
   
   
       5 . The processing method of  claim 4 , further comprising setting the value of an OR-bit to ‘one’ if a predetermined term of the plurality of terms evaluates to true. 
   
   
       6 . The processing method of  claim 5 , further comprising setting the value of the OR-bit to ‘zero’ if the predetermined term of the plurality of terms does not evaluate to true. 
   
   
       7 . The processing method of  claim 6 , further comprising, in a conjunct comprising an OR clause, OR'ing the result of each OR operation with the current value of an OR register. 
   
   
       8 . The processing method of  claim 7 , further comprising, in the event that the OR register has a value of ‘one’ and an OR conjunct register is set to ‘one’, evaluating the conjunct to true and short-circuiting to a next conjunct. 
   
   
       9 . The processing method of  claim 8 , further comprising joining an AND operation and the next conjunct and rolling the value of the OR register up to the AND register by AND'ing the value of the OR register with the value of the AND register. 
   
   
       10 . The processing method of  claim 9 , further comprising, in the event that the OR-bit has a value of ‘zero’ when the AND operation is processed, changing the AND-bit to a value of ‘zero’. 
   
   
       11 . The processing method of  claim 10 , further comprising setting the final value of the Boolean expression to false, if the AND-bit has a value of ‘zero’, and short circuiting the remainder of the Boolean expression. 
   
   
       12 . A device polling unit for finding new devices, assigning addresses to those devices, polling those devices for their current states, and updating a random-access memory with those states, the device polling unit comprising:
 a maximum device address electrically-erasable programmable read-only memory, wherein the electrically-erasable programmable read-only memory is operable for storing the highest address of all known devices on a system, wherein the electrically-erasable programmable read-only memory comprises an increment line that increments its value by one whenever it is asserted and a plurality of output lines that continuously output its value;   an n-bit incrementing register, wherein the n-bit incrementing register is operable for holding an n-bit number representing a current address of a device being polled, wherein the n-bit incrementing register comprises a reset line that sets the register to ‘zero’ whenever it is asserted, and wherein the n-bit incrementing register further comprises an increment line and a plurality of output lines that continuously output its value to an AND unit and a current address encoder; and   wherein the device polling unit operates in a continuous loop after it is started.   
   
   
       13 . The device polling unit of  claim 12 , wherein, if a new device is found and a new device found line is asserted, the device polling unit assigns a system address to the new device via direct parallel communication or serially via a new address encoder. 
   
   
       13 . The device polling unit of  claim 12 , wherein, if a new device is not found, the n-bit incrementing register is incremented, the device polling unit polls the device corresponding to an address in the register, and the device polling unit copies the device's current state into the random-access memory. 
   
   
       14 . A device interface unit for listening for new device seek, new address, state enable, and control line assertions and determining whether or not there is work to do as a result of such assertions, the device interface unit comprising:
 a new device electrically-erasable programmable read-only memory, wherein the new device electrically-erasable programmable read-only memory comprises an n-bit store that is initially set to ‘one’, and wherein, when a new device seek line is asserted, the n-bit store asserts a new device found line.   
   
   
       15 . The device interface unit of  claim 14 , further comprising an address decoder, wherein, if the n-bit store is set, it allows an address passed on a new address line to be placed in an n-bit address electrically-erasable programmable read-only memory and the n-bit store to be cleared. 
   
   
       16 . The device interface unit of  claim 15 , further comprising a control word decoder, wherein the control word decoder is operable for reading serial bits off of a control line, and wherein, if an address matches the address in the n-bit address electrically-erasable programmable read-only memory, a plurality of control bits output to a device controller to change its state. 
   
   
       17 . The device interface unit of  claim 16 , further comprising an address and state encoder, wherein the address and state encoder is operable for reading bits in parallel that represent the address and state of the device and serially outputs the bits to a receiver.