Semiconductor memory device allowing high-speed data reading

Abstract

Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.

1 . A semiconductor memory device, comprising:
 a plurality of memory blocks, arranged in alignment, each having static memory cells arranged in rows and columns, each of the memory blocks including a first subarray and a second subarray each including (i) static memory cells arranged in rows and columns and (ii) a plurality of bit line pairs, arranged corresponding to the respective memory cell columns, each being connected with the static memory cells of a corresponding column;   a sense amplifier arranged, for each of said memory blocks, in common to the first and second subarrays for differentially amplifying potentials of a first sense node and a second sense node when activated;   a first data line pair arranged, for each of the memory blocks, corresponding to said first subarray;   a second data line pair arranged, for each of said memory blocks, corresponding to said second subarray;   a first column selection circuit arranged, for each of said memory blocks, corresponding to said first subarray for coupling a bit line pair of a selected column of said first subarray to said first data line pair according to a received column selection signal when said first subarray is selected;   a second column selection circuit arranged, for each of said memory blocks, corresponding to said second subarray for coupling a bit line pair corresponding to a selected column of said second subarray to said second data line pair according to a received column selection signal when said second subarray is selected;   a first connection control circuit arranged for each of said memory blocks, for coupling said first data line pair to the first and second sense nodes of said sense amplifier according to at least a subarray selection signal;   a second connection control circuit arranged for each of said memory blocks, for coupling said second data line pair to the first and second sense nodes of said sense amplifier according to at least said subarray selection signal; and   a read global data line arranged in common to the sense amplifier of each of said plurality of memory blocks, for transferring data from a selected sense amplifier provided for a selected memory block.   
   
   
       2 . The semiconductor memory device according to  claim 1 , wherein
 said first connection control circuit includes   a first gate circuit for receiving a subarray specifying signal selecting the second subarray of said subarray selection signal and a sense activation signal for activating said sense amplifier; and   a first connection gate for coupling said first data line pair to the first and second sense nodes of said sense amplifier according to an output signal of said first gate circuit, and   said second connection control circuit includes   a second gate circuit for receiving a subarray specifying signal selecting the first subarray of said subarray selection signal and said sense activation signal; and   a second connection gate for coupling said second data line pair to the first and second sense nodes of said sense amplifier according to an output signal of said second gate circuit, and   a data line pair arranged for a selected subarray of the first and second subarrays is coupled to the first and second sense nodes of said sense amplifier before a sense operation by said sense amplifier.   
   
   
       3 . The semiconductor memory device according to  claim 2 , wherein
 each of the first and second connection gates includes a P-channel insulated gate field effect transistor.   
   
   
       4 . The semiconductor memory device according to  claim 1 , further comprising
 precharge circuits, arranged for the first and second data line pairs, respectively, each precharging a corresponding data line pair to a predetermined potential in a standby state of the memory blocks.   
   
   
       5 . The semiconductor memory device according to  claim 1 , further comprising
 a precharge circuit arranged for one of the first and second data line pairs, for precharging the data line pairs to a predetermined potential in a standby state of the memory blocks, wherein   the first and second connection control circuits respectively couple the first and second data line pairs commonly to the first and second sense nodes of said sense amplifier in the standby state of said memory blocks.   
   
   
       6 . A semiconductor memory device, comprising:
 a plurality of memory blocks, arranged corresponding to one data bit, each including first and second subarrays each including a plurality of static memory cells arranged in rows and columns and a plurality of bit line pairs, arranged corresponding to respective memory cell columns, each being connected with the memory cells of a corresponding column;   first and second data line pairs arranged, for each of the memory blocks, corresponding to the first and second subarrays, respectively;   a first column selection circuit arranged, for each of said memory blocks, corresponding to said first subarray for coupling a bit line pair of a selected column of said first subarray to said first data line pair according to a received column selection signal;   a second column selection circuit arranged, for each of said memory blocks, corresponding to said second subarray for coupling a bit line pair of a selected column of said second subarray to said second data line pair according to a received column selection signal;   a data line selection circuit arranged, for each of said memory blocks, in a column circuit region arranged between and in alignment with the first and second subarrays for selecting one of said first and second data line pairs according to at least a subarray selection signal selecting a subarray;   a sense read circuit arranged, for each of said memory blocks, in said column circuit region for amplifying data applied via said data line selection circuit when activated;   an internal write circuit arranged, for each of said memory blocks, in said column circuit region between the first and second subarrays for transmitting internal write data to a data line pair selected by said data line selection circuit; and   a global data bus arranged in common to said plurality of memory blocks and coupled in common to the sense read circuit and the internal write circuit of each of said memory blocks, for transferring internal data including said internal write data.   
   
   
       7 . The semiconductor memory device according to  claim 6 , wherein
 said global data bus includes a write global data line coupled to said internal write circuit for transferring said internal write data and a read global data line coupled to said sense read circuit for transferring an output signal of the sense read circuit being activated.   
   
   
       8 . The semiconductor memory device according to  claim 6 , wherein
 said global data bus is arranged extending over said plurality of memory blocks and said column circuit region.   
   
   
       9 . The semiconductor memory device according to  claim 6 , wherein
 said sense read circuit includes   a sense amplifier arranged in said column circuit region in a position substantially equal in distance to the first and second subarrays, for amplifying data transferred via a data line pair selected by said data line selection circuit, and   a read drive circuit for driving said global data bus according to an output signal of said sense amplifier.