Method of testing memory device

Abstract

A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed in which when an entry information is input, an entry circuit generates an output upon discrimination that said memory device is satisfying conditions for performing test, and when an output of the entry circuit is generated and a memory arrangement of the memory device is in a write enable state, a gate circuit generates an output to activate a buffer circuit, by which the internal signal is written to the memory arrangement by being connected to a data write input of the memory arrangement via the buffer circuit, then reading the written data to the outside from the memory arrangement, and performing the measurement related to the internal signal by detecting data change points.

1 . A semiconductor memory device comprising:
 a memory cell array,   a set of data input or output pins,   an entry circuit generating an output upon discrimination that said memory device is satisfying conditions for performing a test when an entry information is input;   a data read or write circuit performing a data read or write operation between said memory cell array and said data input or output pins,   a signal generation circuit generating an internal signal that takes a high level and a low level cyclically,   a test circuit controlling in a test mode said data read or write circuit to write said levels of said internal signal into said memory cell array in response to an output of said entry circuit and a write enable signal, said write enable signal being cycled at a rate higher than the cycle of said internal signal; and   an output control circuit coupled to said data read or write circuit to read said data in said memory cell array and to supply said data to said data input or output pins, said data being indicative of a pair of change points, each of said change points being responsive to a change of said internal signal between said high and low levels thereof.   
   
   
       2 . A semiconductor memory device comprising:
 a memory cell array,   a data pin,   a write circuit having an output coupled to said array to write data and an input coupled to said pin,   a control circuit having an internal signal generation circuit, a gate circuit and an entry circuit,   wherein said gate circuit operatively couples selected one of said pin or said internal signal generation circuit to an input of the write circuit in response to an condition signal of the entry circuit, and wherein contents written in said array represent cycles of the internal signal.   
   
   
       3 . A semiconductor memory device comprising:
 a memory cell array;   a set of data input or output pins;   a data read or write circuit performing a data read or write operation between said memory cell array and said input or output pins;   a signal generation circuit generating an internal signal that takes a high level and a low level cyclically, and   a test circuit controlling in a test mode said data read or write circuit to write at least two data changes of said internal signal into said memory cell array in response to a write enable signal.   
   
   
       4 . The semiconductor memory device as claimed in  claim 3 , wherein the cycle of said write enable signal is higher than the cycle of said internal signal. 
   
   
       5 . The semiconductor memory device as claimed in  claim 3 , wherein the read or write circuit comprises;
 an input control part transferring in the data read and write operation a write data to the memory cell array from the input or output pins; and   an internal signal buffer transferring in the test mode the internal signal to the memory cell array through the input control part.