Delay circuit and delay synchronization loop device

Abstract

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

1 . A semiconductor device having a delay circuit,
 the delay circuit comprising:   a first delay line circuit having a plurality of stages of delay units;   a second delay line circuit having a plurality of stages of delay units;   a plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit, said transfer circuits respectively receiving outputs of said stages of the delay units of said first delay line circuit to control the transfer of the outputs of said delay units to associated stages of the delay units of said second delay line circuit;   said delay unit of each stage of said first delay line circuit inverting a signal supplied to said delay units and outputting the inverted signal;   the delay unit of each stage of said second delay line circuit, including a logic circuit receiving an output signal of the transfer circuit associated with the delay unit and an output signal of a preceding stage and outputting the result of logical operation of the input signals to a following stage,   one of a plurality of the transfer circuits, receiving respective outputs of odd-numbered stages of delay units of said first delay line circuit, is selected by a corresponding control signal;   one of a plurality of transfer circuits, receiving respective outputs of even-numbered stages of delay units of said first delay line circuit, is selected by a corresponding control signal; and   the rise timing and the fall timing of an output signal of said second delay line circuit are variably set with respect to the rising and fall of the signal supplied to said first delay line circuit.   
   
   
       2 . A semiconductor device having a delay circuit, the delay circuit comprising:
 a first delay line circuit having a plurality of stages of delay units;   a second delay line circuit having a plurality of stages of delay units;   a plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit, said transfer circuits respectively receiving outputs of said stages of the delay units of said first delay line circuit to control the transfer of the outputs of said delay units to associated stages of the delay units of said second delay line circuit;   said delay unit of each stage of said first delay line circuit inverting a signal supplied to said delay units and outputting the inverted signal;   the delay unit of each stage of said second delay line circuit, including a logic circuit receiving an output signal of the transfer circuit associated with the delay unit and an output signal of a preceding stage and outputting the result of logical operation of the input signals to a following stage,   in case the control signal supplied to the transfer circuit associated with a given one of the even-numbered stages and to the transfer circuit associated with a given one of the odd-numbered stages is activated, the control signals supplied to respective transfer circuits downstream of said transfer circuit are activated.   
   
   
       3 . A semiconductor device having a delay locked loop circuit,
 The delay locked loop circuit comprising:   a first delay line circuit receiving an input clock signal;   a second delay line circuit for performing fine phase adjustment of an output signal based on the rising of the clock signal output from said first delay line circuit;   a third delay circuit for performing fine phase adjustment of an output signal based on the falling of the clock signal output from said first delay line circuit;   a multiplexing circuit receiving an output signal of said second delay line circuit and an output signal of said third delay circuit and outputting an output clock signal multiplexed from said two output signals supplied thereto;   a first phase detection circuit receiving said input clock signal and an output clock signal of said multiplexing circuit to detect the phase difference of the rising edges thereof;   a second phase detection circuit receiving said input clock signal and an output clock signal of said multiplexing circuit to detect the phase difference of the falling edges thereof;   a first counter for counting the result of phase detection by said first phase detection circuit;   a second counter for counting the result of phase detection by said second phase detection circuit;   a first selection circuit for outputting a control signal for adjusting the rise timing in said first delay line circuit based on a count output of said first counter; and   a second selection circuit for outputting a control signal for adjusting the fall timing in said first delay line circuit based on a count output of said second counter;   wherein said first delay line circuit is a delay circuit comprising:   a plurality of stages of delay units; a plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit,   said transfer circuits respectively receiving outputs of said stages of the delay units of said first delay line circuit to control the transfer of the outputs of said delay units to associated stages of the delay units of said second delay line circuit;   said delay unit of each stage of said first delay line circuit inverting a signal supplied to said delay units and outputting the inverted signal.   
   
   
       4 . The semiconductor device according to  claim 3 ,
 wherein said first delay line circuit outputs a signal with plural rising edges of respective different phases, generated from said input signal, and   another signal with plural falling edges of respective different phases, generated from an inverted version of said input signal.   
   
   
       5 . A semiconductor device having a delay locked circuit for generating an internal clock signal synchronized with an input clock signal, said delay locked loop circuit comprising:
 a first phase detection circuit for comparing the rising phase of said input clock signal and the rising phase of said internal clock signal;   a second phase detection circuit for comparing the falling phase of said input clock signal to the falling phase of said internal clock signal;   first and second variable delay circuits having delays thereof varied by the results of phase comparison in said first and second phase detection circuits;   the rinsing and falling of said internal clock signal, obtained on multiplexing outputs of said first and second variable delay circuits, being adjustable independently of each other;   a mode decision circuit for deterring the clock period and an initial delay value by comparison;   a first selection circuit for selecting for control of which of said first and second variable delay circuits the results of phase comparison by said first and second phase detection circuits are to be used; and   a second selection circuit for switching, in multiplexing signals output from said first and second variable delay circuits to generate said internal clock signal, between the use of the rise and the fall of signals output from said first and second variable delay circuits for the rising of said internal clock signal and the use of the raise and fall of signal output from said first and second variable delay circuits for the fall of said internal clock signal, based on the result of mode decision.   
   
   
       6 . The semiconductor device according to  claim 5 ,
 wherein at least one of said first and second phase detection circuits is composed by a circuit for detecting the duty ratio of said internal clock signal.   
   
   
       7 . The semiconductor device according to  claim 5 , further comprising;
 a circuit for detecting the duty ratio of said internal clock signal; and   a selector circuit for operating, based on the result of mode decision and an input duty ratio detection enable signal, for selecting for control of which of said first and second variable delay circuits the results of decision by said first and second phase detection circuits and said duty ratio detection circuit are to be used.   
   
   
       8 . A semiconductor device having a delay locked loop circuit, said delay locked loop circuit comprising;
 a first phase detection circuit for comparing the phase of the rise of said input clock signal and the phase of the rise of said internal clock signal;   a second phase detection circuit for comparing the phase of the fall of said input clock signal and the phase of the fall of said internal clock signal;   first and second variable delay circuits, the delay of which is varied by the results of phase detection circuits,   wherein the rise and fall of said internal clock signal, obtained on multiplexing the outputs of said first and second variable delay circuits, are adjustable independently of each other; and   a mode decision circuit for determining the clock period and an initial delay value by comparison,   wherein said first phase detection circuit includes a switching circuit for selecting an inverting or no-inverting output result of the comparison of the phase of rising of said internal clock signal with the phase of rising of said input clock signal to compare the phase of rising of said internal clock signal with the phase of fall of said input clock signal by the result of mode decision,   said second phase detection circuit includes a switching circuit for selecting an inverting of non-inverting output result of the comparison of the phase of rising of said internal clock signal with the phase of rising of said input clock signal to compare the phase of falling of said internal clock signal to the phase of rising of said reference clock signal by the result of mode decision, and   there being provided a circuit for inverting the phase of said internal clock based on said result of mode decision is provided.   
   
   
       9 . A semiconductor device having a delay locked loop circuit, said delay locked loop circuit comprising:
 a variable delay circuit receiving an input signal and outputting the signal with a variable delay of the rise timing and the fall timing of said input signal;   a multiplexing circuit for outputting an output signal the pulse width of which is prescribed by the rising and the fall of the signal delayed by said variable delay circuit; and   a control circuit for comparing the phase of rise and the fall of said input signal and the phase of rise and the fall of said output signal for variable controlling the delay time of said variable delay circuit based on the respective results of phase comparison;   said multiplexing circuit including a circuit for switching between the decision of the rise timing and the fall timing of said output signal of said variable delay circuit, based on the fall and the rise of the output signal from said variable delay circuit;   said control circuit including a circuit for switching between varying the delay value of the rise timing and the fall timing of the output signal in said variable delay circuit based on the result of comparison of the rising phase of said input signal and the rising phase of said output signal and on the result of comparison of the falling phase of said input signal and the falling phase of said output signal and varying the delay value of the fall timing and the rise timing of the output signal in said variable delay circuit based on the result of comparison of the rising phase of the input signal and the rising phase of the output signal and on the result of comparison of the fall phase of said input signal and the fall phase of said output signal.