US2008135953A1PendingUtilityA1
Noise reduction in semiconductor devices
Est. expiryDec 7, 2026(~0.4 yrs left)· nominal 20-yr term from priority
Inventors:Domagoj Siprak
H10P 30/225H10P 30/21H10D 64/01348H10P 30/208H10P 30/204H10D 30/62H10D 86/00H10D 84/0181H10D 84/0172H10D 84/038H10D 64/691H10P 30/28
50
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Claims
Abstract
Some embodiments discussed relate to an integrated circuit and methods of making it, comprising a semiconductor substrate and a support layer disposed on the semiconductor substrate, wherein the support layer is doped using a noise-reducing dopant and a gate insulator disposed on the support layer, and a gate stack disposed on the gate insulator.
Claims
exact text as granted — not AI-modified1 . An integrated circuit, comprising:
a semiconductor substrate; a support layer disposed on the semiconductor substrate, wherein the support layer is doped using a noise-reducing dopant; a gate insulator disposed on the support layer; and a gate stack disposed on the gate insulator.
2 . The integrated circuit in claim 1 , wherein the gate insulator includes a material with dielectric constant greater than the dielectric constant of the support layer.
3 . The integrated circuit of claim 2 , wherein the noise-reducing dopant includes a material selected from the group consisting of Fluorine, Chlorine, ClF 5 , SiCl 4 , Hydrogen, Deuterium, XeF2, Xenon hexafluoride XeF 6 and NF3.
4 . The integrated circuit of claim 2 , wherein the support layer includes a material selected from the group consisting of silicon dioxide, nitrided silicon oxide and fluorinated silicon oxide.
5 . The integrated circuit of claim 2 , wherein the support layer includes a first portion having a first thickness and a second portion having a second thickness, wherein the first portion is configured to support a first circuit adapted to operate under a constant bias condition and the second portion is configured to support a second circuit adapted to operate under a switching bias condition.
6 . The integrated circuit of claim 2 , wherein the gate insulator includes a layer having first thickness at a first portion of the gate insulator and a second thickness at a second portion of the gate insulator.
7 . The integrated circuit of claim 2 , wherein the gate insulator includes a material selected from the group consisting of Al 2 O 3 , GD 2 O 3 , Yb 2 O 3 , Dy 2 O 3 , Nb 2 O 5 , Yb 2 O 3 , La 2 O 3 , TiO 2 , Ta 2 O 5 , SrTiO 3 , Ba x Sr 1-x , TiO 3 , Zr x Si 1-x O y , HfSiON, HfZrO x , Al x Zr 1-x O 2 , nitrided silicon oxide and silicon nitride Si 3 N4.
8 . The integrated circuit of claim 2 , wherein the gate stack a material selected from the group consisting of a poly silicon gate, a fully silicided gate and a metal gate.
9 . The integrated circuit of claim 2 , wherein the substrate is implanted with a second noise-reducing dopant.
10 . The integrated circuit of claim 9 , wherein the second noise reducing dopant includes a material selected from the group consisting of Fluorine, Boron difluoride BF2, Boron trifluoride BF3, PF 3 , PF 5 , AsF 3 , AsF 5 , SbF 3 , SbF 5 , Chlorine, Boron trichloride BCl3, ClF 5 , SiF, SiCl 4 , Hydrogen, Deuterium, XeF2, and Xenon hexafluoride XeF6.
11 . The integrated circuit of claim 1 , further comprising:
at least one of a planar CMOS FET, a fin FET having two conducting channels and a multi-gate FET having more than two conducting channels.
12 . A method of fabricating an integrated circuit, comprising:
providing a semiconductor substrate; forming a support layer disposed over the semiconductor wafer; doping the support layer using a noise-reducing dopant; forming a gate insulator disposed over the support layer, wherein the dielectric constant of the gate insulator is greater than the dielectric constant of the support layer; and forming a gate stack disposed over the gate insulator.
13 . The method of claim 12 includes determining a thickness of the support layer adapted to minimize the total flicker noise contribution by the gate insulator and the support layer, wherein the ratio is determined by minimizing the equation for the spectral noise power density S id :
S
id
=
K
1
·
{
N
t
(
hk
)
·
(
ɛ
Support
ɛ
hk
)
2
·
1
3
·
T
D
}
+
K
2
·
{
N
t
(
hk
)
·
(
z
-
(
ɛ
Support
ɛ
hk
)
2
)
·
y
·
T
D
[
1
-
y
+
1
3
·
y
2
]
}
where, K1=is a constant based on the frequency dependence of traps located in the high-k.
K2=is a constant based on the frequency dependence of traps located in the support layer.
N t (hk)=the number of effective traps in the high-k layer.
“z” =ratio between N t (Support) and N t (hk), where N t (Support) is the number of effective trapped electrons in the SiO2 layer (support layer) due to noise reduction by using noise-reducing dopants,
T D
y=ratio of the thickness of the gate support layer and the thickness of dielectric T D
14 . The method of claim 12 , wherein forming the support layer includes forming a first portion of the support layer having a first thickness including a first circuit operating under a constant bias condition and forming a second portion of the support layer having a second thickness including a second circuit operating under a switched bias condition.
15 . The method of claim 12 , further comprising:
removing an oxide layer covering the semiconductor substrate using a wet Hydrogen Fluoride (HF) dip process prior to forming the support layer.
16 . The method of claim 15 , wherein removing the oxide layer includes cleaning the semiconductor substrate after the HF dip using a cleaning agent including ammonia hydrogen peroxide water.
17 . The method of claim 16 , wherein removing the native oxide layer further comprises cleaning the semiconductor substrate using a cleaning agent including hydrogen fluoride (HF) vapor.
18 . The method of claim 12 , wherein forming the support layer disposed over the semiconductor substrate includes forming the support layer by thermally growing silicon dioxide.
19 . The method of claim 14 , wherein forming the first portion of the support layer includes thermally growing over the substrate layer having a first portion doped with a first doping agent, and forming the second portion of the support layer includes thermally growing over the substrate layer having a second portion doped with a second doping agent.
20 . The method of claim 12 , wherein forming the gate insulator disposed over the support layer includes forming a first portion having a first thickness and forming a second portion having a second thickness.
21 . The method of claim 18 , wherein forming the support layer disposed over the semiconductor substrate includes forming a nitrided silicon oxide layer within the support layer.
22 . The method of claim 12 , wherein doping the support layer using a noise-reducing dopant includes doping the support layer using a material selected from the group consisting of Fluorine, Chlorine, ClF 5 , SiCl 4 , Hydrogen, Deuterium, XeF2, Xenon hexafluoride XeF6, and NF3.
23 . The method of claim 12 , wherein forming the gate insulator disposed over the support layer includes forming the gate insulator using a material selected from the group consisting of Al 2 O 3 , GD 2 O 3 , Yb 2 O 3 , Dy 2 O 3 , Nb 2 O 5 , Yb 2 O 3 , La 2 O 3 , TiO 2 , Ta 2 O 5 , SrTiO 3 , Ba x Sr 1-x TiO 3 , Zr x Si 1-x O y , Hf x Si 1-x O y , HfSiON, HfZrO x , Al x Zr 1-x O 2 , nitrided silicon oxide and silicon nitride (Si3N4).
24 . The method of claim 12 , wherein forming the gate stack disposed over the gate insulator layer includes forming the gate stack including at least one of a poly silicon gate, a fully silicided gate and a metal gate.
25 . The method of claim 21 , wherein the nitrided silicon oxide layer is formed by a plasma nitridation process.
26 . The method of claim 12 , wherein providing the gate stack disposed over the support layer includes providing the gate stack including at least one of a poly silicon gate, a fully silicided gate and a metal gate.
27 . The method of claim 12 , further comprising:
implanting the semiconductor substrate using a second noise-reducing dopant.
28 . The method of claim 12 , implanting the semiconductor substrate using the second noise reducing dopant includes implanting the semiconductor substrate with a material selected from the group consisting of Fluorine, Boron difluoride BF2, Boron trifluoride BF3, PF 3 , PF 5 , AsF 3 , AsF 5 , SbF 3 , SbF 5 , Chlorine, Boron trichloride BCl3, CIF 5 , SiF, SiCl 4 , Hydrogen, Deuterium XeF2, and Xenon hexafluoride XeF6.
29 . The method of claim 12 , wherein forming the support layer further comprises annealing the semiconductor substrate to treat crystal damage and removing a native oxide by HF vapor cleaning in a chamber followed by thermally growing the support layer in the chamber.
30 . A method of fabricating an integrated circuit, comprising:
providing a semiconductor substrate having a first portion and second portion, wherein the first portion is implanted with a first noise-reducing dopant and the second portion is implanted with a second noise reducing dopant; thermally growing a support layer disposed over the first portion and the second portion of the semiconductor substrate; doping the support layer using a third noise-reducing dopant; forming a gate insulator disposed over the support layer, wherein the dielectric constant of the gate insulator is greater than the dielectric constant of the support layer; and forming a gate stack disposed over the gate insulator.
31 . The method of claim 30 , wherein forming the gate insulator disposed over the support layer includes forming a first portion having a first thickness and forming a second portion having a second thickness.
32 . An integrated circuit, comprising:
a semiconductor substrate; a gate insulator supported by the semiconductor substrate, the gate insulator including a dielectric layer with a graded dielectric constant; and a gate stack disposed on the gate insulator.
33 . The integrated circuit of claim 32 , wherein the dielectric layer is adapted to reduce flicker noise in the integrated circuit under switched bias condition.
34 . The integrated circuit of claim 32 , wherein the dielectric constant decreases from the gate to the substrate.
35 . The integrated circuit of claim 34 , comprising:
a support layer disposed on the semiconductor substrate doped with a noise-reducing dopant.
36 . The integrated circuit of claim 34 , wherein the dielectric layer is doped with a noise-reducing dopant.
37 . The integrated circuit of claim 34 , wherein the dielectric layer includes a dielectric layer having a continuously varying dielectric constant.
38 . The integrated circuit of claim 34 , wherein the dielectric layer includes a plurality of dielectric layers stacked between the substrate and the gate stack.Join the waitlist — get patent alerts
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