MIM transistor

Abstract

The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.

1 . A transistor comprising:
 a conducting layer having a thickness of between 1 and 5 atoms; and   an insulated gate being formed on at least a portion of the conducting layer.   
   
   
       2 . The transistor of  claim 1 , wherein the conducting layer is formed of metal. 
   
   
       3 . The transistor of  claim 1 , further comprising:
 a first electrode and a second electrode, and the insulated gate being positioned between the first and second electrodes.   
   
   
       4 . The transistor of  claim 3 , wherein the conducting layer extends between the first electrode and the second electrode. 
   
   
       5 . The transistor of  claim 1 , wherein the conducting layer is on an insulating layer such that the insulating layer is between the conducting layer and a semiconductor substrate. 
   
   
       6 . The transistor of  claim 5 , wherein the semiconductor substrate under the transistor is connected to a determined voltage. 
   
   
       7 . The transistor of  claim 1 , further comprising:
 a surface in contact with the conducting layer having a nanoroughness.   
   
   
       8 . The transistor of  claim 1 , wherein the insulated gate includes a gate and an insulating layer between the gate and the conducting layer. 
   
   
       9 . The transistor of  claim 1 , wherein the transistor is integrated into a semiconductor chip. 
   
   
       10 . A transistor comprising:
 a conductive layer having a section with a thickness equal to or less than 5 atoms;   a gate on the section of the conductive layer having the thickness equal to or less than 5 atoms; and   an insulating layer between the gate and the conductive layer.   
   
   
       11 . The transistor of  claim 10 , further comprising:
 a first electrode and a second electrode on the conductive layer, the gate and insulating layer positioned between and spaced apart from the first electrode and the second electrode.   
   
   
       12 . The transistor of  claim 10 , wherein the gate and the conductive layer are made of metal. 
   
   
       13 . The transistor of  claim 10 , further comprising:
 a substrate under the conductive layer, the substrate comprising a semiconductor substrate and a substrate insulating layer, and the substrate insulating layer positioned between the conductive layer and the semiconductor substrate.   
   
   
       14 . The transistor of  claim 10 , wherein the conductive layer is on a nano-roughened support surface. 
   
   
       15 . The transistor of  claim 14 , further comprising:
 an insulating layer having the nano-roughened support surface.   
   
   
       16 . The transistor of  claim 9 , wherein the insulating layer has a thickness that is sufficiently small such that at least a portion of the conductive layer is depleted so that the transistor is in a non-conducting state when an electric field is applied via the insulated gate. 
   
   
       17 . A structure comprising:
 a first transistor including a first conducting layer having a thickness of between 1 and 5 atoms and a first insulated gate being formed on at least a portion of the first conducting layer; and   a second transistor including a second conducting layer having a thickness of between 1 and 5 atoms and a second insulated gate being formed on at least a portion of the second conducting layer, the second transistor adjacent to the first transistor;   wherein first and second semiconductor substrate portions under the first and second transistors, respectively, have opposite conductivity types, the first and second semiconductor substrate portions are adjacent one another and configured to be biased so that a junction between the semiconductor substrate portions is non-conducting.   
   
   
       18 . The structure of  claim 17 , where a first material forming the first semiconductor substrate portion is N-type doped silicon and a second material forming the second semiconductor substrate portion is P-type doped silicon. 
   
   
       19 . The structure of  claim 17 , wherein the first material physically contacts the second material. 
   
   
       20 . The structure of  claim 17 , wherein a continuous conducting layer on an insulator forms the first and second conducting layers.