Manufacturing method of non-volatile memory

Abstract

A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.

What is claimed is: 
     
         1 . A method of fabricating a non-volatile memory, comprising:
 forming a mask layer over a substrate;   forming a trench in the mask layer and exposing a portion of the substrate;   forming a gate structure in the trench, wherein the gate structure comprises a gate dielectric layer, a select gate and a cap layer;   removing the mask layer;   forming a tunneling dielectric layer over the substrate;   forming floating gates on both sidewalls of the gate structure;   forming doped regions in the substrate on both sides of the gate structure;   forming a inter-gate dielectric layer on the substrate; and   forming a control gate on the substrate.   
     
     
         2 . The method as claimed in  claim 1 , wherein the step of forming the floating gate comprises:
 forming a conductive layer on the substrate; and   performing an anisotropic etching process on the conductive layer to form the floating gate.   
     
     
         3 . The method as claimed in  claim 1 , wherein the step of forming the select gate comprises:
 forming a conductive material layer on the gate dielectric layer;   etching the conductive layer to remove a portion of the conductive material layer until a top surface of the conductive material layer is lower than that of the mask layer.   
     
     
         4 . The method as claimed in  claim 1 , further comprising removing the cap layer after the step of forming the doped region but before the step of forming the inter-gate dielectric layer. 
     
     
         5 . The method as claimed in  claim 1 , wherein the step of forming the gate dielectric layer comprises performing chemical vapor deposition process. 
     
     
         6 . The method as claimed in  claim 1 , wherein the step of forming the cap layer comprises:
 forming a dielectric material layer on the select gate; and   removing the dielectric material layer on the mask layer.   
     
     
         7 . The method as claimed in  claim 6 , wherein the step of removing the dielectric material layer on the mask layer comprises performing an etching back or a chemical mechanical polishing process. 
     
     
         8 . The method as claimed in  claim 1 , further comprising forming a pad layer before the step of forming the mask layer. 
     
     
         9 . The method as claimed in  claim 1 , wherein the material of the inter-gate dielectric layer comprises silicon oxide/silicon nitride/silicon oxide. 
     
     
         10 . The method as claimed in  claim 1 , wherein the material of the mask layer comprises silicon nitride. 
     
     
         11 . The method as claimed in  claim 1 , wherein the material of the select gate comprises doped poly-silicon. 
     
     
         12 . The method as claimed in  claim 1 , wherein the material of the floating gate comprises doped poly-silicon. 
     
     
         13 . The method as claimed in  claim 1 , wherein the material of the control gate comprises doped poly-silicon.