Architecture and method for parallel embedded block coding

Abstract

The present invention provides a high-speed, memory efficient parallel coding technique for embedded block coding with optimized truncation (EBCOT) used in still image compression. Attributing to parallel processing method and structure, it processes a discrete wavelet transform (DWT) coefficient at a clock cycle without any state variable stored. Therefore, the need of state variable memory can be avoid and the external memory bandwidth can be reduced. With the same cost of chip-area and lower power consumption, the processing rate of this invention is several times higher than conventional schemes. Furthermore, the present invention processes 50 M coefficients per second at 100 MHz and can encode lossless HDTV 720p resolution pictures at 30 fps in real time.

1 - 9 . (canceled) 
   
   
       10 . A coding apparatus processing a DWT coefficient having a plurality of bit-planes in parallel at a time to provide coding information for further coding process, said coding apparatus comprising:
 a Gobang register bank (GRB) module, a compute most significant bit pass (CMP) module, find contribution and coding pass (FC) modules, context formation (CF) modules, a reconfigurable first-in first-out register (RFIFO) module and arithmetic encoder (AE) modules;   wherein there are one said FC module and one said CF module for each bit-plane and at one AE module for every two bit-planes.   
   
   
       11 . The coding apparatus claimed in  claim 10 , wherein said Gobang register bank module is a 2-dimensional shift register bank whereby input DWT coefficients recorded to meet JPEG 2000 scan order. 
   
   
       12 . The coding apparatus claimed in  claim 10 , wherein said compute most significant bit pass module determines a value P c   mc  of target coefficient and computes variables λ s   k , κ s   k  of each coefficient. 
   
   
       13 . The coding apparatus claimed in  claim 10 , wherein said find contribution and coding pass (FC) module determines the coding pass information of target coefficient and PHVD information for said context formation module to compute context. 
   
   
       14 . The coding apparatus claimed in  claim 10 , wherein said context formation module is provided to treat special run-length codes. 
   
   
       15 . The coding apparatus claimed in  claim 10 , wherein said reconfigurable first-in first-out register (RFIFO) module is provided to make the compression process more fluent. 
   
   
       16 . The coding apparatus claimed in  claim 10 , wherein said arithmetic encoder is provided to decrease the hardware requirement and increase the system utilization. 
   
   
       17 . (canceled)