Chip package and fabricating process thereof

Abstract

A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.

1 . A chip package, comprising:
 a carrier, having a carrying surface and a back surface opposite to the carrying surface, the carrier further having a plurality of common contacts in the periphery of the carrying surface;   a chip, disposed on the carrying surface and electrically connected to the carrier;   a plurality of first conductive elements, disposed on the common contacts respectively;   an encapsulation, disposed on the carrying surface and encapsulating the chip; and   a conductive film, disposed over the encapsulation and the first conductive elements, so as to connected to the common contacts via the first conductive elements.   
   
   
       2 . The chip package according to  claim 1 , wherein the first conductive elements comprise a plurality of first solder balls. 
   
   
       3 . The chip package according to  claim 1 , wherein the first conductive elements surround the encapsulation. 
   
   
       4 . The chip package according to  claim 3 , further comprising a conductive bonding layer disposed between the conductive film and the first conductive elements. 
   
   
       5 . The chip package according to  claim 4 , wherein the conductive bonding layer is a solder layer. 
   
   
       6 . The chip package according to  claim 1 , wherein the encapsulation covers the carrying surface and encapsulates the chip and the first conductive elements, and the encapsulation exposes a top portion of each first conductive element. 
   
   
       7 . The chip package according to  claim 6 , wherein the conductive film is directly attached on a top surface of the encapsulation so as to connect with the first conductive elements. 
   
   
       8 . The chip package according to  claim 6 , further comprising a plurality of second conductive elements disposed between the conductive film and the corresponding first conductive elements respectively. 
   
   
       9 . The chip package according to  claim 8 , wherein the second conductive elements comprise a plurality of second solder balls. 
   
   
       10 . The chip package according to  claim 1 , wherein the conductive film is a metal film. 
   
   
       11 . The chip package according to  claim 1 , wherein the carrier is a circuit substrate. 
   
   
       12 . The chip package according to  claim 1 , further comprising a plurality of conductive bumps, the chip being electrically connected with the carrier by a flip chip manner. 
   
   
       13 . The chip package according to  claim 1 , further comprising a plurality of wires connected between the chip and the carrier and encapsulated by the encapsulation. 
   
   
       14 . The chip package according to  claim 1 , further comprising a plurality of third solder balls disposed on the back surface of the carrier, the third solder balls being electrically connected with the chip and/or the first conductive elements via the carrier respectively. 
   
   
       15 . A chip packaging process, comprising:
 providing a carrier which has a carrying surface and a back surface opposite to the carrying surface, the carrier further having a plurality of common contacts in the periphery of the carrying surface;   disposing a chip on the carrying surface and electrically connecting the chip to the carrier;   forming an encapsulation on the carrying surface, wherein the encapsulation encapsulates the chip;   forming a plurality of first conductive elements on the corresponding common contacts; and   providing a conductive film on the encapsulation and electrically connecting the conductive film to the common contacts via the first conductive elements.   
   
   
       16 . The chip packaging process according to  claim 15 , wherein the first conductive elements are fabricated by forming a first solder ball on each common contact respectively. 
   
   
       17 . The chip packaging process according to  claim 15 , further comprising forming a conductive bonding layer between the conductive film and the first conductive elements so as to connect the conductive film to the first conductive elements via the conductive bonding layer. 
   
   
       18 . The chip packaging process according to  claim 17 , wherein the conductive bonding layer is fabricated by coating a solder layer on the conductive film. 
   
   
       19 . The chip packaging process according to  claim 15 , wherein the chip is bonded to the carrier by flip chip bonding technology. 
   
   
       20 . The chip packaging process according to  claim 15 , wherein the chip is bonded to the carrier by wire bonding technology. 
   
   
       21 . The chip packaging process according to  claim 15 , further comprising forming a plurality of second solder balls on the back surface of the carrier, the second solder balls being electrically connected with the chip and/or the first conductive elements via the carrier respectively. 
   
   
       22 . A chip packaging process, comprising:
 providing a carrier which has a carrying surface and a back surface opposite to the carrying surface, the carrier further having a plurality of common contacts in the periphery of the carrying surface;   disposing a chip on the carrying surface and electrically connecting the chip to the carrier;   forming a plurality of first conductive elements on the corresponding common contacts;   forming an encapsulation for covering the carrying surface and encapsulating the chip and the first conductive elements, the encapsulation exposing a top portion of each first conductive element;   providing a conductive film and forming a plurality of second conductive elements on a surface of the conductive film; and   disposing the conductive film over the encapsulation and connecting the second conductive elements to the corresponding first conductive elements, wherein the conductive film is electrically connected to the common contacts via the first conductive elements and the second conductive elements.   
   
   
       23 . The chip packaging process according to  claim 22 , wherein the first conductive elements are fabricated by forming a first solder ball on each common contact respectively. 
   
   
       24 . The chip packaging process according to  claim 22 , wherein the second conductive elements are fabricated by forming a plurality of second solder balls on the conductive film. 
   
   
       25 . The chip packaging process according to  claim 22 , wherein the chip is bonded to the carrier by flip chip bonding technology. 
   
   
       26 . The chip packaging process according to  claim 22 , wherein the chip is bonded to the carrier by wire bonding technology. 
   
   
       27 . The chip packaging process according to  claim 22 , further comprising forming a plurality of third solder balls on the back surface of the carrier, the third solder balls being electrically connected with the chip and/or the first conductive elements via the carrier respectively. 
   
   
       28 . A chip packaging process, comprising:
 providing a carrier which has a carrying surface and a back surface opposite to the carrying surface, the carrier further having a plurality of common contacts in the periphery of the carrying surface;   disposing a chip on the carrying surface and electrically connecting the chip to the carrier;   forming a plurality of first conductive elements on the corresponding common contacts;   forming an encapsulation for covering the carrying surface and encapsulating the chip and the first conductive elements, the encapsulation exposing a top portion of each first conductive element; and   forming a conductive film on a top surface of the encapsulation so as to electrically connect the conductive film to the common contacts via the first conductive elements.   
   
   
       29 . The chip packaging process according to  claim 28 , wherein the first conductive elements are fabricated by forming a first solder ball on each common contact respectively. 
   
   
       30 . The chip packaging process according to  claim 28 , wherein the conductive film is fabricated by spraying a conductive material on the top surface of the encapsulation. 
   
   
       31 . The chip packaging process according to  claim 28 , wherein the chip is bonded to the carrier by flip chip bonding technology. 
   
   
       32 . The chip packaging process according to  claim 28 , wherein the chip is bonded to the carrier by wire bonding technology. 
   
   
       33 . The chip packaging process according to  claim 28 , further comprising forming a plurality of second solder balls on the back surface of the carrier, the second solder balls being electrically connected with the chip and/or the first conductive elements via the carrier respectively.