Self-aligned nanometer-level transistor defined without lithography

Abstract

A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.

1 . An electronic device, comprising:
 an insulating layer formed over a substrate;   a semiconducting layer formed over the insulating layer;   a fin fabricated from a first portion of the semiconducting layer and having a minimum lateral dimension related to a thickness of a dielectric formed over the fin and used to form a dielectric spacer, the fin being doped with a majority carrier of a first type;   a gate region comprised of a semiconducting material and overlying the fin;   a drain region formed from a second portion of the semiconducting layer adjacent to the fin, the drain region being located on a first side of the gate region, the drain region being doped with a majority carrier of a second type; and   a source region formed on a second portion of the semiconducting layer adjacent to the fin, the source region being distal to the drain region and located on a second side of the gate region, the source region being doped with the majority carrier of the second type.   
   
   
       2 . The electronic device of  claim 1  wherein the semiconducting layer is chosen to have a ( 100 ) lattice orientation. 
   
   
       3 . The electronic device of  claim 1  wherein the semiconducting layer is chosen to have a particular lattice orientation. 
   
   
       4 . The electronic device of  claim 1  wherein the width of the fin is in a range of approximately 30 nm to 100 nm. 
   
   
       5 . The electronic device of  claim 1  wherein the substrate is comprised of a silicon-on-insulator (SOI) material. 
   
   
       6 . An electronic device, comprising:
 a fin fabricated from a first portion of a semiconducting layer and having a minimum lateral dimension related to a thickness of a dielectric spacer formed over the fin;   a gate region comprised of a semiconducting material and overlying the fin;   a drain region formed from a second portion of the semiconducting layer adjacent to the fin and located on a first side of the gate region; and   a source region formed from a second portion of the semiconducting layer adjacent to the fin and located on a second side of the gate region, the source region being doped with the majority carrier of the second type.   
   
   
       7 . The electronic device of  claim 6  wherein the semiconducting layer is formed over a dielectric material. 
   
   
       8 . The electronic device of  claim 6  wherein the semiconducting layer is a portion of a silicon-on-insulator (SOI) material. 
   
   
       9 . The electronic device of  claim 6  wherein the fin includes a dopant having a majority carrier of a first type and the drain and source regions each include a dopant having a majority carrier of a second type. 
   
   
       10 . The electronic device of  claim 6  wherein the width of the fin is in a range of approximately 30 nm to 100 nm. 
   
   
       11 . A method of forming a fin in an electronic device, the method comprising:
 providing a substrate having a base, an insulative layer, and a semiconducting layer;   forming a pedestal region from a portion of the semiconducting layer;   surrounding the pedestal region with a first dielectric layer having an uppermost surface being substantially coplanar with an uppermost surface of the pedestal region,   forming a second dielectric material over a first uppermost portion of the pedestal region leaving an exposed uppermost portion of the pedestal region not covered by the second dielectric material;   forming a third dielectric material over the second dielectric material and the exposed portion of the pedestal region;   etching regions of the third dielectric material that are substantially parallel to a face of the substrate thereby leaving a first dielectric spacer, the first dielectric spacer overlying a protected portion of the pedestal region;   substantially removing the second dielectric material; and   etching substantially all portions of the pedestal region that are not laterally in proximity to or underlying the protected portion, thereby forming a fin.   
   
   
       12 . The method of  claim 11  further comprising:
 forming a fourth dielectric layer substantially over the fin and first dielectric layer;   etching regions of the fourth dielectric material that are substantially parallel to a face of the substrate thereby leaving a set of second dielectric spacers substantially covering an exposed sidewall of the first dielectric layer; and   filling an opening proximate to the fin with polysilicon.   
   
   
       13 . The method of  claim 12  wherein the polysilicon is planarized to a level substantially coplanar with the uppermost surface of the first dielectric layer. 
   
   
       14 . The method of  claim 11  wherein the substrate is comprised of a silicon-on-insulator (SOI) material. 
   
   
       15 . The method of  claim 11  wherein the substrate is comprised of a SIMOX material. 
   
   
       16 . The method of  claim 11  further comprising:
 doping the fin with a dopant having a first type of majority carrier; and   doping remaining portions of the pedestal region distal to the protected portion with a dopant having a second type of majority carrier.   
   
   
       17 . The method of  claim 11  further comprising selecting a material for the second dielectric layer and a material for the third dielectric layer to have dissimilar etching characteristics.