Single transistor floating body dram cell having recess channel transistor structure

Abstract

Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first conductivity type spaced apart from the source region and a floating body of a second conductivity type between the barrier layer and the source region and the drain region. The floating body includes a recess region between the source region and the drain region.

1 . A single transistor floating body dynamic random access memory (DRAM) cell, comprising:
 a semiconductor substrate;   a barrier layer on the semiconductor substrate; and   a recess channel transistor on the barrier layer, the recess channel transistor comprising:   a source region of a first conductivity type;   a drain region of the first conductivity type spaced apart from the source region;   a floating body of a second conductivity type between the barrier layer and the source region and the drain region, the floating body including a recess region between the source region and the drain region; and   a gate electrode in the recess region.   
   
   
       2 . The single transistor floating body DRAM cell of  claim 1 , further comprising:
 an isolation layer on the semiconductor substrate and contacting the barrier layer and the floating body, wherein the isolation layer has a bottom surface positioned at a level relative to the semiconductor substrate no higher than a top surface of the barrier layer and a top surface positioned at a level higher than a top surface of the floating body.   
   
   
       3 . The single transistor floating body DRAM cell of  claim 1 , wherein the recess region has a bottom surface positioned at a level relative to the semiconductor substrate lower than bottom surfaces of the source region and the drain region. 
   
   
       4 . The single transistor floating body DRAM cell of  claim 3 , wherein the recess channel transistor further comprises a gate dielectric layer between the gate electrode and the floating body. 
   
   
       5 . The single transistor floating body DRAM cell of  claim 4 , wherein the gate electrode has a bottom surface positioned at a level lower than the bottom surfaces of the source region and the drain region. 
   
   
       6 . The single transistor floating body DRAM cell of  claim 1 , wherein the first conductivity type is an N-type and the second conductivity type is a P-type. 
   
   
       7 . The single transistor floating body DRAM cell of  claim 1 , wherein the first conductivity type is a P-type and the second conductivity type is an N-type. 
   
   
       8 . The single transistor floating body DRAM cell of  claim 1 , wherein the barrier layer comprises a high concentration impurity region of the first conductivity type and/or an oxide layer. 
   
   
       9 . A single transistor floating body dynamic random access memory (DRAM) cell, comprising:
 an integrated circuit substrate;   a barrier layer on the substrate; and   a recess channel transistor on the barrier layer, the recess channel transistor comprising:   an N-type source region;   an N-type drain region spaced apart from the source region;   a P-type floating body between the barrier layer and the source region and the drain region, the floating body including a recess region extending across the floating body between the source region and the drain region; and   a gate electrode in the recess region.   
   
   
       10 . The single transistor floating body DRAM cell of  claim 9 , further comprising:
 a gate dielectric layer between the gate electrode and the floating body; and   an isolation layer on the substrate and contacting the barrier layer and the floating body, wherein the isolation layer has a bottom surface positioned at a level relative to the substrate no higher than a top surface of the barrier layer and a top surface positioned at a level higher than a top surface of the floating body;   wherein the gate electrode fills the recess region.   
   
   
       11 . The single transistor floating body DRAM cell of  claim 10 , wherein the recess region has a bottom surface positioned at a level relative to the substrate lower than bottom surfaces of the source region and the drain region. 
   
   
       12 . The single transistor floating body DRAM cell of  claim 10 , wherein the gate electrode has a bottom surface positioned at a level lower than the bottom surfaces of the source region and the drain region.