Non-Volatile Memory Including Insulated Gate Bipolar Transistors And Charge Trapping Layer Containing Silicon and Nitrogen

Abstract

A memory block of a semiconductor memory array where the semiconductor memory array is a NOR array, a NAND array, or an AND array includes a bit line, memory cells where each memory cell has a floating gate including a charge trapping layer containing silicon and nitrogen, a metal-oxide-semiconductor select transistor that separates said bit line and said memory cells, a semiconductor region enclosed within the drain of said select transistor with a conductivity type that is opposite to that of said drain, and a semiconductor well region shared by said select transistor and said memory cells.

1 . A memory block of a semiconductor memory array, the semiconductor memory array being a NOR array, a NAND array, or an AND array, the memory block comprising:
 a bit line;   memory cells, each memory cell having a floating gate comprising a charge trapping layer containing silicon and nitrogen;   a metal-oxide-semiconductor select transistor that separates said bit line and said memory cells;   a semiconductor region enclosed within the drain of said select transistor with a conductivity type that is opposite to that of said drain; and   a semiconductor well region shared by said select transistor and said memory cells.   
   
   
       2 . The memory block of  claim 1  wherein said charge trapping layer comprises a multilayer charge trapping medium containing nanocrystals. 
   
   
       3 . The memory block of  claim 1 , further comprising means to electrically connect said semiconductor region and said drain. 
   
   
       4 . The memory block of  claim 3 , wherein said means comprises a metal-oxide-semiconductor transistor capable of being set to the on or off state independent of the state of said select transistor. 
   
   
       5 . The memory block of  claim 3 , wherein said means comprises a resistor. 
   
   
       6 . The memory array of  claim 3 , wherein said memory array is built with a semiconductor manufacturing process which uses more than one well. 
   
   
       7 . The memory array of  claim 3 , wherein said memory array is built with a silicon-on-insulator technology. 
   
   
       8 . A memory block of a semiconductor memory array of a NAND type, the memory block comprising:
 a bit line;   memory cells, each memory cell having a floating gate comprising a charge trapping layer containing silicon and nitrogen;   a metal-oxide-semiconductor select transistor that separates said bit line and said memory cells;   a semiconductor region enclosed within the drain of said select transistor with a conductivity type that is opposite to that of said drain; and   a semiconductor well region shared by said select transistor and said memory cells.   
   
   
       9 . The memory block of  claim 8  wherein said charge trapping layer comprises a multilayer charge trapping medium containing nanocrystals. 
   
   
       10 . The memory block of  claim 8 , further comprising means to electrically connect said semiconductor region and said drain. 
   
   
       11 . The memory block of  claim 10 , wherein said means comprises a metal-oxide-semiconductor transistor capable of being set to the on or off state independent of the state of said select transistor. 
   
   
       12 . The memory block of  claim 10 , wherein said means comprises a resistor. 
   
   
       13 . The memory array of  claim 10 , wherein said memory array is built with a semiconductor manufacturing process which uses more than one well. 
   
   
       14 . The memory array of  claim 10 , wherein said memory array is built with a silicon-on-insulator technology.