High density semiconductor memory device and method for manufacturing the same

Abstract

Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged.

1 . A high density semiconductor memory device, comprising:
 source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and   a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots.   
     
     
         2 . The high density semiconductor memory device of  claim 1 , wherein the nanodots are formed using a silicon compound as a basal body. 
     
     
         3 . The high density semiconductor memory device of  claim 2 , wherein the silicon compound basal body comprises one selected from the group consisting of silicon oxide, silicon nitride and silicon carbon. 
     
     
         4 . The high density semiconductor memory device of  claim 1 , wherein the nanodots are formed using a chargeable material as a basal body. 
     
     
         5 . The high density semiconductor memory device of  claim 1 , further comprising a gate dielectric layer formed over the floating gate. 
     
     
         6 . The high density semiconductor memory device of  claim 1 , further comprising:
 a tunneling dielectric layer disposed between the substrate of the channel region and the floating gate; and   a control gate disposed over the floating gate.   
     
     
         7 . The high density semiconductor memory device of  claim 1 , wherein the channel region comprises silicon and the source and drain electrodes comprise metal silicide. 
     
     
         8 . The high density semiconductor memory device of  claim 1 , wherein the source and drain electrodes comprise a material selected from the group consisting of erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolinium (Gd), terbium (Tb) and cerium (Ce) when an electron is used as a majority carrier. 
     
     
         9 . The high density semiconductor memory device of  claim 1 , wherein the source and drain electrodes comprise a material selected from the group consisting of platinum (Pt), lead (Pb) and iridium (Ir) when a hole is used as a majority carrier. 
     
     
         10 . The high density semiconductor memory device of  claim 1 , wherein the substrate comprises one of a bulk silicon substrate and a silicon-on-insulator (SOI) substrate. 
     
     
         11 . A method for manufacturing a high density semiconductor memory device, the method comprising the steps of:
 a) forming a channel region and source and drain electrodes in a substrate, the source and drain electrodes forming a Schottky junction with the channel region;   b) forming a tunneling dielectric layer over the substrate;   c) forming a floating gate over the tunneling dielectric layer, the floating gate comprising a plurality of nanodots;   d) forming a control gate over the floating gate; and   e) etching the control gate, the floating gate and the tunneling dielectric layer to expose the source and drain electrodes.   
     
     
         12 . The method of  claim 11 , further comprising the step of:
 f) forming a gate dielectric layer over the floating gate.   
     
     
         13 . The method of  claim 11 , wherein the nanodots are formed using a silicon compound as a basal body. 
     
     
         14 . The method of  claim 13 , wherein the silicon compound basal body is formed of one selected from the group consisting of silicon oxide, silicon nitride and silicon carbon. 
     
     
         15 . The method of  claim 11 , wherein the nanodots are formed using a chargeable material as a basal body. 
     
     
         16 . The method of  claim 11 , wherein the channel region is formed of silicon, and the source and drain electrodes are formed of metal silicide. 
     
     
         17 . The method of  claim 11 , wherein the source and drain electrodes are formed of a material selected from the group consisting of erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolinium (Gd), terbium (Tb) and cerium (Ce) when an electron is used as a majority carrier. 
     
     
         18 . The method of  claim 11 , wherein the source and drain electrodes are formed of a material selected from the group consisting of platinum (Pt), lead (Pb) and iridium (Ir) when a hole is used as a majority carrier. 
     
     
         19 . The method of  claim 11 , wherein the substrate comprises one of a bulk silicon substrate and an SOI substrate.