Mosfet structure with ultra-low k spacer

Abstract

A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

1 . A field effect transistor comprising:
 a substrate comprising source/drain extensions positioned laterally adjacent a channel region;   a gate oxide layer on said channel region and overlapping portions of said source/drain extensions;   a gate conductor on said gate oxide layer and comprising a sidewall; and   a sidewall spacer positioned laterally adjacent said sidewall and on a corresponding one of said source/drain extensions,   wherein said sidewall spacer comprises:
 a first dielectric layer comprising a vertical portion positioned adjacent said sidewall and a horizontal portion positioned above said corresponding source/drain extension; and 
 a second dielectric layer positioned adjacent said vertical portion and above said horizontal portion, 
 wherein said first dielectric layer has a permittivity value of less than three. 
   
   
   
       2 . The field effect transistor according to  claim 1 , all the limitations of which are incorporated by reference, wherein said second dielectric layer comprises one of a nitride layer and an oxide layer. 
   
   
       3 . The field effect transistor according to  claim 1 , all the limitations of which are incorporated by reference, wherein said first dielectric layer comprises one of a carbon-doped oxide, a hydrogen-doped oxide, an aromatic polymer, a parylene, a fluorine-doped amorphous carbon, and an organosilicate material. 
   
   
       4 . The field effect transistor according to  claim 1 , all the limitations of which are incorporated by reference, wherein said first dielectric layer comprises one of a porous oxide, a porous silicate, a porous organosilicate, and a porous SiLK™. 
   
   
       5 . The field effect transistor according to  claim 1 , all the limitations of which are incorporated by reference, wherein said first dielectric layer is approximately 20 nm thick and wherein said second dielectric layer is approximately 20 nm thick. 
   
   
       6 . A method of forming a field effect transistor, said method comprising:
 forming a gate oxide layer and a gate conductor on a channel region and overlapping a source/drain extension;   forming a sacrificial layer adjacent a sidewall of said gate conductor and above said source/drain extension;   forming a permeable low-K dielectric layer adjacent said sacrificial layer and above said source/drain extension; and   heating said sacrificial layer,   wherein said sacrificial layer volatizes into molecules during said heating process and wherein said molecules diffuse through said permeable low-K dielectric layer, thereby, forming a gap.   
   
   
       7 . The method according to  claim 6 , all the limitations of which are incorporated by reference, further comprising forming an additional dielectric layer adjacent said permeable low-K dielectric layer; wherein said additional dielectric layer comprises one of a nitride material and an oxide material. 
   
   
       8 . The method according to  claim 6 , all the limitations of which are incorporated by reference, wherein said forming of said sacrificial layer comprises:
 depositing an organic material over said gate conductor and said source/drain extension; and   etching said organic material to expose a portion of said source/drain extension,   wherein said organic material is thermally stable up to approximately 300° Celsius and volatizes into said molecules that can diffuse through said permeable low-K dielectric layer at temperatures above approximately 400° Celsius.   
   
   
       9 . The method according to  claim 8 , all the limitations of which are incorporated by reference, wherein said organic material comprises at least one of a poly(styrene), poly(ester), poly(methacrylate), poly(acrylate) and poly(glycol), poly(amide), poly(norbornene), poly(diene), poly(alkene), poly(acrylamide), poly(methacrylamide), poly(vinylether), poly(vinyl alcohol), poly(ketone), poly(acetal), poly(vinylester), and poly(carbonate). 
   
   
       10 . The method according to  claim 6 , all the limitations of which are incorporated by reference, wherein said forming of said permeable low-K dielectric layer comprises depositing one of an organo silicate glass, an organo silsesquioxane, a hydrido-silsesquioxanes, a porous silicon oxide, a porous silicon nitride, a porous silicon oxynitride, and a siloxane over said sacrificial layer. 
   
   
       11 . A method of forming a field effect transistor, said method comprising:
 forming a gate oxide layer and a gate conductor on a channel region and overlapping a source/drain extension;   forming a first dielectric layer comprising a vertical portion positioned adjacent a sidewall of said gate conductor and a horizontal portion positioned above said source/drain extension; and   forming a second dielectric layer positioned adjacent said vertical portion and above said horizontal portion,   wherein said first dielectric layer has a permittivity value of less than three.   
   
   
       12 . The method according to  claim 11 , all the limitations of which are incorporated by reference, wherein said forming of said first dielectric layer and said forming of said second dielectric layer comprise:
 depositing a dielectric material over said gate conductor and said source/drain extension;   etching said dielectric material to form said vertical portion adjacent said sidewall and said horizontal portion above said source/drain extension;   depositing one of a nitride layer and an oxide layer over said first dielectric layer; and   etching said one of a nitride layer and an oxide layer to form said second dielectric layer.   
   
   
       13 . The method according to  claim 12 , all the limitations of which are incorporated by reference, wherein said dielectric material comprises one of a carbon-doped oxide, a hydrogen-doped oxide, an aromatic polymer, a parylene, a fluorine-doped amorphous carbon, and an organosilicate and wherein said dielectric material has a permittivity value of less than three. 
   
   
       14 . The method according to  claim 12 , all the limitations of which are incorporated by reference, wherein said dielectric material comprises:
 a matrix material comprising one of an oxide, a silicate, an organosilicate, and an organic material; and   a pore generating material,   wherein said method further comprises after said depositing and said etching of said dielectric material, performing a rapid thermal anneal thereby forming a porous first dielectric layer having a permittivity value of less than three.