US2008128159A1PendingUtilityA1
Method for manufacturing a printed circuit board that mounts an integrated circuit device thereon and the printed circuit board
Est. expiryDec 19, 2023(expired)· nominal 20-yr term from priority
Inventors:Koji Ito
H10W 70/688Y10T29/49169H05K 3/242Y10T29/49155Y10T29/4913H05K 1/0393Y10T29/49147H05K 2203/1545H05K 2203/0191H05K 2203/175H05K 1/0268H05K 3/28Y10T29/49204H05K 3/243H05K 2201/0397
50
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Claims
Abstract
A tape substrate includes IC lands electrically connected to pins of a driver IC (integrated circuit), circuit board terminal lands electrically connected to an external circuit board, test lands for testing the driver IC mounted on the tape substrate, and a plating terminal used for plating the land. The test lands are arranged in a matrix. The plating terminal is disposed so as to surround the IC lands, the circuit board terminal lands, and the test lands.
Claims
exact text as granted — not AI-modified1 . A printed circuit board, comprising:
a plurality of device lands that are capable of being electrically connected to pins of an integrated circuit device when the integrated circuit device is mounted on the printed circuit board; a plurality of terminal lands that are capable of being electrically connected to terminals of an external device when the integrated circuit device is mounted on the printed circuit board; a plurality of test lands used for performing an operational test of the integrated circuit device when the integrated circuit device is mounted on the printed circuit board; a plating terminal used for plating the terminal lands; and a wiring pattern including a plurality of traces that electrically connect the device lands to the terminal lands, the test lands and the plating terminal, wherein all the test lands are disposed outside an area interposed between the plurality of terminal lands and the plurality of device lands.
2 . The printed circuit board according to claim 1 , wherein the plurality of test lands, the plurality of terminal lands and the plurality of device lands are disposed in parallel along a same direction, with a row of the plurality of terminal lands disposed in a center between a row of the plurality of test lands and a row of the plurality of device lands, and the traces of the wiring pattern directly connect the test lands and the terminal lands and directly connect the terminal lands and the device lands.
3 . The printed circuit board according to claim 1 , wherein the plating terminal is formed at both end portions of an area including the plurality of device lands, the plurality of terminal lands, and the plurality of test lands.
4 . The printed circuit board according to claim 3 , wherein the plating terminal surrounds the plurality of device lands, the plurality of terminal lands, and the plurality of test lands.
5 . The printed circuit board according to claim 1 , wherein the plurality of the terminal lands are plated with nickel and solder, and the plurality of the device lands and the test lands are plated with tin by displacement plating.
6 . The printed circuit board according to claim 1 , that mounts the integrated circuit device thereon, wherein the pins of the integrated circuit device are electrically connected to the plurality of device lands when the integrated circuit device is mounted on the printed circuit board.Join the waitlist — get patent alerts
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