Operand Multiplexor Control Modifier Instruction in a Fine Grain Multithreaded Vector Microprocessor

Abstract

The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.

1 . A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:
 a controller configured to receive instructions comprising swizzle instructions and arithmetic instructions, each swizzle instruction being associated with an arithmetic instruction, wherein:
 if the instruction is a swizzle instruction the controller is configured to set controls of one or more multiplexors coupled with a register file and a vector unit, wherein the setting of the multiplexor controls is configured to determine an arrangement of content in one or more registers providing input to the vector unit; and 
 if the instruction is an arithmetic instruction the controller is configured to allow transfer of contents of registers associated with the arithmetic instruction to the vector unit, wherein the contents are rearranged by the one or more multiplexors during transfer of the contents from the register file to the vector unit based on the setting of the multiplexor controls. 
   
   
   
       2 . The design structure of  claim 1 , wherein the design structure comprises a netlist, which describes the controller. 
   
   
       3 . The design structure of  claim 1 , wherein the design structure resides on the storage medium as a data format used for the exchange of layout data of integrated circuits. 
   
   
       4 . The design structure of  claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications. 
   
   
       5 . A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:
 a system comprising a plurality of processors communicably coupled with one another, wherein each processor comprises:
 a register file comprising a plurality of registers; 
 at least one vector unit for executing arithmetic instructions; 
 one or more multiplexors coupled with the register file and the at least one vector unit, wherein the multiplexors are configured to transfer contents of one or more registers in the register file to the at least one vector unit; and 
 a controller configured to receive swizzle instructions and arithmetic instructions, each swizzle instruction being associated with an arithmetic instruction, wherein:
 if the instruction is a swizzle instruction the controller is configured to set controls of the one or more multiplexors, wherein the setting of the multiplexor controls is configured to determine an arrangement of content in one or more registers providing input to the vector unit; and 
 if the instruction is an arithmetic instruction the controller is configured to allow transfer of contents of registers associated with the arithmetic instruction to the vector unit, wherein the contents are rearranged by the one or more multiplexors during transfer of the contents from the register file to the vector unit based on the setting of the multiplexor controls. 
 
   
   
   
       6 . The design structure of  claim 5 , wherein the design structure comprises a netlist, which describes the system. 
   
   
       7 . The design structure of  claim 5 , wherein the design structure resides on the storage medium as a data format used for the exchange of layout data of integrated circuits. 
   
   
       8 . The design structure of  claim 5 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.