Memory card

Abstract

The present invention provides a memory card for use with an electronic device. The memory card comprises an input/output (I/O) interface for coupling the memory card to the electronic device and a card controller electrically coupled to the I/O interface. In particular, the card controller comprises a plurality of engines configured to operate in different formats. The card controller further comprises a means for detecting the format of the electronic device and generating a response signal containing the format of the electronic device. A micro-controller is electrically coupled to the plurality of engines, wherein the micro-controller activates an appropriate engine from the plurality of engines to transfer data based on the response signal. Furthermore, the memory comprises a memory module electrically coupled to the plurality of engines for storing data. One advantage of the memory card is that it enables a user to store and transfer data in various formats.

What is claimed is: 
     
         1 . A memory card for use with an electronic device, the memory card comprising:
 an input/output (I/O) interface for coupling the memory card to the electronic device;   a card controller electrically coupled to the I/O interface, the card controller comprising:
 a plurality of engines configured to operate in different formats; 
 format detecting means for detecting the format of the electronic device and generating a response signal indicating the format of the electronic device; and 
 a micro-controller electrically coupled to the plurality of engines and the format detecting means, wherein when the micro-controller receives the response signal, it activates an appropriate engine from the plurality of engines to transfer data based on the response signal; and 
 a memory module electrically coupled to the plurality of engines for storing data. 
   
     
     
         2 . The memory card of  claim 1 , wherein the plurality of engines have a first engine operating at a predetermined system frequency, the first engine comprising:
 a command module coupled to the micro-controller, wherein the command module is configured to transmit command packets to the electronic device or receive command packets from the electronic device; and   a data transfer module coupled to the micro-controller and the command module, wherein the micro-controller controls the data transfer module to transfer data packets between the memory module and the electronic device depending on the type of command packet received from the electronic device.   
     
     
         3 . The memory card of  claim 2 , wherein the command module comprises:
 a command encoder coupled to the micro-controller, wherein the command encoder is configured to encode a command signal from the micro-controller into a command packet that is to be transmitted to the electronic device; and   a command control engine coupled to the command encoder, wherein the command control engine is configured to control the format of the command packet that is transmitted to the electronic device;   
     
     
         4 . The memory card of  3 , wherein the command module further comprises a first cyclic redundancy check (CRC) unit coupled to the command control engine, wherein the first CRC unit is configured to protect the content of the command packet in order for the first engine to receive or transmit the command packet correctly. 
     
     
         5 . The memory card of  claim 2 , wherein the data transfer module comprises:
 a half frequency data clocked engine coupled to the micro-controller and the I/O interface, comprising:
 a first internal clock and a second internal clock, wherein the frequency of both first and the second internal clock is half of the predetermined system frequency, wherein the second internal clock is configured to operate at a half-period delay relative to the first internal clock; 
 a positive data capture engine configured to capture data at the positive edge of the first internal clock and second internal clock; 
 a negative data capture engine configured to capture data at the negative edge of the first internal clock and second internal clock; 
 a data storage engine coupled to both the positive and negative data capture engines, comprising:
 a positive data region configured to store the data captured by the positive data capture engine; 
 a negative data region configured to store the data captured by the negative data capture engine; 
 a first data pointer configured to locate the data stored in the positive data region; and 
 a second data pointer configured to locate the data stored in the negative data region; 
 wherein the data stored in both the positive and negative data regions are packed into a data packet; 
 
   a data multiplexer engine coupled to the data storage engine, wherein the data multiplexer engine is configured to receive the data packet from the data storage engine and then stores the data packet in the memory module; and   a data control engine coupled to the micro-controller, wherein the data control engine is configured to control the format of the data packet.   
     
     
         6 . The memory card of  claim 5 , wherein the data transfer module further comprises an internal buffer coupled to the data multiplexer engine and the memory module, wherein the internal buffer serves as a temporary data storage for the data packet. 
     
     
         7 . The memory card of  claim 5 , wherein the data transfer module further comprises a second CRC unit coupled to the data control engine, wherein the second CRC unit is configured to check the integrity of the data packet in order for the first engine to transmit or receive the data packet correctly. 
     
     
         8 . The memory card of  claim 6 , wherein the data transfer module further comprises a data convert engine coupled to the micro-controller and I/O interface, wherein the data convert engine is configured to convert data packet in parallel format from the internal buffer to serial format for the I/O interface, and wherein the data convert engine is configured to convert data packet in serial format from the I/O interface to parallel format for the internal buffer. 
     
     
         9 . The memory card of  claim 1 , wherein the plurality of engines configured to operate in different formats are selected from the group consisting of Secure Digital (SD), Serial Peripheral Interface (SPI), Memory Stick (MS) or Memory Stick Pro (MS Pro). 
     
     
         10 . The memory card of  claim 1  further comprises a card-side interface that serves as a mechanical connection between the I/O interface and the card controller. 
     
     
         11 . The memory card of  claim 10 , wherein the card controller is coupled to the card-side interface via a serial to parallel interface, wherein the serial to parallel interface converts serial data format from the card-side interface to parallel data format for processing by the plurality of engines. 
     
     
         12 . The memory card of  claim 1 , wherein the means for detecting the format of the electronic device can be a card mode and clock control unit. 
     
     
         13 . The memory card of  claim 1  further comprises a memory-side interface that serves as a mechanical connection between the card controller and the memory module. 
     
     
         14 . The memory card of  claim 13 , wherein the card controller is coupled to the memory-side interface via a memory interface. 
     
     
         15 . The memory card of  claim 1 , wherein the card controller further comprises a power on reset (POR) unit that resets the internal circuitry of the card controller when the memory card is first coupled to the electronic device. 
     
     
         16 . The memory card of  claim 1 , wherein the card controller further comprises a regulator that converts supply voltage to a suitable voltage level for use by the internal circuitry of the card controller. 
     
     
         17 . The memory card of  claim 1 , wherein the memory module can be a plurality of NAND Flash memory chips. 
     
     
         18 . The memory card of  claim 1 , wherein the I/O interface can be coupled to the electronic device via an adaptor unit.