US2008124883A1PendingUtilityA1

Semiconductor structure and method of manufacture

Assignee: IBMPriority: Nov 2, 2005Filed: Nov 16, 2007Published: May 29, 2008
Est. expiryNov 2, 2025(expired)· nominal 20-yr term from priority
H10D 84/641H10D 84/617H10D 62/137H10D 10/821H10D 8/50H10D 84/221
50
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

Claims

exact text as granted — not AI-modified
1 . A method of forming a structure, comprising:
 providing a substrate including a first layer;   forming a doped region in the first layer;   forming a first reachthrough in the first layer;   forming a second layer on the first layer;   forming a second doped region in the second layer, wherein the second doped region is formed at a different depth than the first doped region; and   forming a second reachthrough in the second layer, the second reachthrough being used to link the first reachthrough as a reachthrough for a near side device.   
   
   
       2 . The method of  claim 1 , further comprising forming a third layer on the second layer. 
   
   
       3 . The method of  claim 1 , wherein the first layer is an upper surface of the substrate and the second layer is an epitaxial film. 
   
   
       4 . The method of  claim 2 , wherein the third layer is an epitaxial film. 
   
   
       5 . The method of  claim 1 , wherein the first doped region is a cathode plate for a P-i-N diode or high breakdown NPN BHT subcollector and the second doped region is a subcollector for a high performance bipolar transistor. 
   
   
       6 . The method of  claim 1 , further comprising forming a P+ film over an upper surface of the second region. 
   
   
       7 . The method of  claim 6 , further comprising forming a metal contact over the P+ film. 
   
   
       8 . A method of forming a structure, comprising:
 forming a first subcollector in a substrate;   forming a first epitaxial layer on the substrate;   forming a second subcollector in the first epitaxial layer;   forming a second epitaxial layer on the first epitaxial layer;   forming a first reachthrough extending from the first subcollector to an upper surface of the second epitaxial layer; and   forming a second reachthrough extending from the second subcollector to the upper surface of the second epitaxial layer.   
   
   
       9 . The method of  claim 8 , wherein the first reachthrough is formed over the first subcollector. 
   
   
       10 . The method of  claim 8 , further comprising forming a metal contact over the first reachthrough. 
   
   
       11 . The method of  claim 10 , wherein the first reachthrough provides a conducting channel between the metal contact and the first subcollector.

Join the waitlist — get patent alerts

Track US2008124883A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.