US2008124835A1PendingUtilityA1

Hermetic seal and reliable bonding structures for 3d applications

Assignee: IBMPriority: Nov 3, 2006Filed: Nov 3, 2006Published: May 29, 2008
Est. expiryNov 3, 2026(~0.3 yrs left)· nominal 20-yr term from priority
H10W 90/722H10W 80/312H10W 46/00H10W 90/00
51
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Claims

Abstract

A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Claims

exact text as granted — not AI-modified
1 - 6 . (canceled) 
   
   
       7 . A method for sealing a microelectronic structure and providing mechanical stress endurance, comprising:
 providing and positioning a plurality of chips on at least two wafers being electrically connected to a semiconductor structure at a plurality of locations, the chips comprising outer edges;   depositing a length of continuous bonding material on each chip on a planar surface thereof defining a perimeter substantially adjacent to the outer edge of each chip;   connecting at least one support column on each of the chips and within the perimeter of each chip, each support column extending outwardly;   positioning the chips in overlapping relation such that the bonding material and the support columns are in mating relation to each other, respectively;   compressing the chips and thereby the bonding material together;   heating the bonding material to form a seal about the perimeter of the chips whereby a bonded chip structure is formed;   positioning a plurality of support columns between multiple layers in the chips to provide support between the layers;   depositing a bonding material along a perimeter adjacent to an outer edge of the wafer;   compressing the bonding material on each of the wafers together with each other in mating relation; and   heating the mated bonding material to form a seal and a bonded wafer structure.   
   
   
       8 . (canceled) 
   
   
       9 . (canceled)

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